MEMS Integration Engineer

nEye.ai, a well-funded optical switch startup, is poised to revolutionize the future of data centers. nEye's MEMS-based silicon photonics optical circuit switches (OCS) eliminate critical bottlenecks in AI processing by enabling direct optical connections among thousands of GPUs and memory units. The company's SuperSwitch is an ultra-low power consumption, high radix, compact chip-scale design, offering hyperscale data centers enhanced performance, efficiency, and scalability. Job Overview We are seeking a highly technical MEMS Integration Engineer to bridge the gap between our internal design engineering teams and external foundry partners. This role requires a strong foundry process engineering background combined with the strategic oversight of a foundry manager. You will be responsible for owning the technical execution of product development, driving new product introduction (NPI), and ensuring the successful transfer of our Silicon Photonics and MEMS processes to high-volume manufacturing. Your success will ensure seamless integration and alignment with nEye's device specifications, optimizing device performance, reducing unit costs, and maximizing wafer yield through continuous improvement. Key Responsibilities Product Development & Transfer: Partner closely with design engineering and fabs to define, develop, and refine process flows for new MEMS products. Oversee the end-to-end NPI lifecycle, from process transfer to external foundries, ensuring manufacturability and repeatability. Act as the primary technical interface between nEye’s design team and foundry integration engineers. Foundry Process Engineering: Design, document, and execute end-to-end MEMS process flows. Integrate diverse modules (lithography, etch, thin films) into a cohesive fabrication sequence. Develop and maintain rigorous process specifications, utilizing deep expertise in diverse fabrication modules including lithography, etch, and deposition to ensure seamless integration. Serve as the subject-matter expert for back-end bonding technologies (anodic, fusion, eutectic, hybrid) to achieve long-term hermeticity; manage surface preparation and activation; manage CTE mismatch and bond-induced stress. Lead the development and integration of through-silicon vias (TSVs) for advanced device packaging. Manage foundry tape-out activities, ensuring successful execution and alignment with project timelines. Own the technical execution of the fabrication schedule, foundry activities and deliverables to ensure on-time wafer out. Monitor statistical process control (SPC) and address out-of-control (OOC) events immediately. Yield & Failure Analysis: Analyze metrology data (SEM, AFM, CSAM, IR, profilometry) to identify failure modes in the bond interface (e.g., voids, delamination) and implement corrective actions. Track, analyze, and report on key process and device performance metrics, identifying opportunities for performance uplift and process simplification. Lead root cause analysis (RCA) and 8D reporting for process deviations or hardware failures, working closely with foundry FA labs. Drive continuous improvement plans (CIP) to optimize device performance, reduce unit costs, and maximize wafer yield. Required Experience BS, MS, or PhD in Electrical Engineering, Mechanical Engineering, MEMS, Applied Physics, Materials Science, or a related technical field. 5+ years of hands-on experience in foundry process engineering, MEMS, or CMOS process development and integration. Proven track record managing tape-outs and taking products through the NPI lifecycle into high-volume manufacturing within a foundry environment. Proven track record of architecting and executing successful, end-to-end MEMS process flows, balancing thermal budgets and material compatibility across complex modules. Deep expertise in wafer-to-wafer integration, surface activation, alignment tolerances, and bonding techniques (fusion, anodic, eutectic, hybrid). Experience with TSV integration, cavity SOI processing, and management of TSV-induced thermo-mechanical stress in bonded wafers. Proficiency in SPC methodologies, yield analysis software, and a solid understanding of cleanroom practices. Deep familiarity using AI tools (LLMs, copilots) to accelerate engineering workflows, debugging and problem-solving. Preferred Experience Experience leading foundry-facing engineering initiatives. Layout & DFM proficiency in LEdit, Cadence, or KLayout. Ability to lead mask floor-planning, including strategic placement of process control monitors, alignment marks, and dicing streets. Mastery of quality control methods, including 6-sigma, 8D, and FMEA. Ability to thrive in a fast-paced, zero-to-one startup environment with minimal supervision. nEye.ai is an Equal Opportunity Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, age, sex, sexual orientation, gender identity, national origin, disability, protected veteran status, or any other characteristic protected by law. We may use artificial intelligence tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us. Starting salary and title will depend on, and be commensurate with, relevant experience, skills, training, education, market demands, and the ultimate job duties and requirements. #J-18808-Ljbffr nEye.ai