Senior Silicon Architect
$218k - $237kQualifications Bachelor’s degree in Electrical Engineering, Computer Engineering or a related field and 4 years of experience in the job offered or in a Silicon Architect-related occupation. Position requires the following: 4 years of experience in Microarchitecture design such as pipelines, caches, TLBs, execution systems, memory; 4 years of experience in System-level optimization or SoC-level optimization such as performance, power, reliability, cost; 4 years of experience in IP integration or Silicon IP integration for System-on-Chip (SoC) designs; 4 years of experience in RTL code analysis such as Verilog or VHDL; 4 years of experience in Technical leadership such as project planning and driving decisions with stakeholders; 1 year of experience in Machine Learning (ML) accelerator architecture design. Minimum Qualifications Bachelor’s degree in Electrical Engineering, Computer Engineering or a related field and 4 years of experience in the job offered or in a Silicon Architect-related occupation. Position requires the following: 4 years of experience in Microarchitecture design such as pipelines, caches, TLBs, execution systems, memory; 4 years of experience in System-level optimization or SoC-level optimization such as performance, power, reliability, cost; 4 years of experience in IP integration or Silicon IP integration for System-on-Chip (SoC) designs; 4 years of experience in RTL code analysis such as Verilog or VHDL; 4 years of experience in Technical leadership such as project planning and driving decisions with stakeholders; 1 year of experience in Machine Learning (ML) accelerator architecture design. About The Job The US base salary range for this full‑time position is $218,000 - $237,000 plus 15% bonus target plus equity plus benefits determined by role, level, and location. Individual pay is determined by additional factors, including job‑related skills, experience, and relevant education or training. Learn more about benefits at Google. Position reports to the Google Mountain View, CA office and may allow for a hybrid schedule as per Google policy. Artificial intelligence will be one of humanity’s most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high‑quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority. We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort. Responsibilities Lead the definition of chip IP architectures, memory hierarchy, interconnect fabrics, and IP integration to meet product requirements. Utilize high‑level performance and power models to guide architectural decisions and conduct detailed trade‑off analyses to optimize for system‑level goals. Create and maintain detailed architectural specification documents that guide micro‑architecture and design teams throughout the project lifecycle. Collaborate with software, product management, and physical design teams to ensure the hardware architecture is feasible, aligns with software needs, and meets all product requirements. Drive the technical evaluation, selection, and integration strategy for key third‑party IP cores and technologies; research emerging technologies and industry trends to influence and contribute to the long‑term silicon and system architecture roadmap. Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form. #J-18808-Ljbffr Google
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...ARM, RISC-V, x86). About the job As a Lead CPU and Performance Architect, you'll be the key contributor to improve processor instruction... ...implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. #J-18808-Ljbffr GoogleSeniorFull time- Architect Labs is a frontier AI lab for chip design. We build AI models and tools for on-demand custom ASICs at scale. Our goal is to co... ...paradigms. Born out of Stanford Research, our team blends AI with Silicon with a founding team from Anthropic, Google DeepMind, Meta...SeniorNight shift
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SoC Power Architect, Devices and Services, Silicon Mountain View, CA, USA; San Diego, CA, USA Advanced Experience owning outcomes and decision making,... ...roadmap decisions. Represent the status of SoC power to senior leadership team. Information collected and processed...Full timeWorldwide- As a Silicon Photonics PIC Architect you will engage in the development of advanced silicon photonics integrated circuits‑based products. You will take responsibility for the design of complex photonic devices and interconnects, as well as systems-on-chip, from design through...
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...job Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct‑to‑consumer... ...efficiency, and integration. As a Performance, Power and Thermal Architect, you will help drive Mobile SoC Architecture optimized for...Full timeWorldwide$120k - $275k
Silicon Micro-Architect and RTL Designer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run...Full timeWork experience placementWork at officeLocal areaRemote workMonday to FridayFlexible hours3 days per week- ...Technical Lead Sr Principal Software Engineer to develop and oversee the base software for high-performance automotive computing. This senior role entails strategic leadership in platform architecture, technical governance, and mentoring junior engineers. With strong...Senior
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