CPU Memory Design Engineer

Job Details Job Description: The CPU Circuit Technology team is looking for a highly motivated and experienced individual to join our team as a CPU Memory Design Engineer. In this role, you will be responsible for designing, developing, and building full‑custom as well as compiler‑based SRAMs, Large Signal Arrays (custom multi‑ported register file), ROMs, custom memories, digital circuits and caches for Intel CPU and SOCs. You will be partnering with and leveraging domain experts across various areas of technology development to develop and deliver high‑quality industry‑leading memory technology collaterals and to drive circuit innovations that enable next‑generation high‑performance, high‑density, low‑power embedded memory designs on advanced CMOS process technologies for Intel CPU and SOCs. This will be a fast‑paced dynamic environment where you will work in the high‑performance, low‑power CPU design team on a wide spectrum of circuit activities including, but may not be limited to: Technical readiness, memory circuit design, characterization and simulations. Cache design, critical path simulations and design custom blocks to meet stringent power/performance/area constraints. Memory path‑finding activities and power, performance and area (PPA) optimization. Memory bit‑cell and complex periphery IC design and automation. Memory array/IP design, memory circuit innovation. Methodology definition tasks as well as executing project schedules. Qualifications Minimum Qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, or a STEM‑related field with 6+ years of experience; or Master's degree with 5+ years of experience; or PhD with 2+ years of experience.
• Proficiency in CMOS circuit design, digital logic optimizations, and circuit trade‑offs for power, performance, and area.
• Expertise in Very Large Scale Integration (VLSI) circuits and design methodologies.

Preferred Qualifications:

• Experience in low‑power implementation techniques and memory design.
• Familiarity with circuit and layout trade‑offs for optimized design.
• Knowledge of EBB design tools, flows and methodologies, and signal integrity analysis.
• Strong analytical and problem‑solving skills, with the ability to prioritize tasks and work in dynamic environments.

Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $164,470.00 - 269,100.00 USD Work Model This role will be eligible for our hybrid work model which allows employees to split their time between working on‑site at their assigned Intel site and off‑site. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. #J-18808-Ljbffr Intel