RTL Design Lead for High-Speed SoC & Memory IP
PHIZENIX
PHIZENIX is seeking an experienced Digital Design Lead to drive RTL design and verification for next-generation semiconductor products. The role leads digital design across high-speed interface and memory IPs, partnering with architecture, verification, and physical design teams to deliver silicon-ready designs. You will mentor design engineers and collaborate with verification, DFT, and physical design teams to meet project schedules, ensuring quality and performance at scale. #J-18808-Ljbffr PHIZENIX
Vacancy posted 3 days ago
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