Senior FPGA Engineer, Cyber

Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century’s most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril’s family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years.ABOUT THE TEAM Anduril Cyber is focused on positioning Anduril as a lead provider of capabilities to enable offensive cyber missions. Cyber is a new business line at Anduril, and relies upon our fleet of autonomous vehicles, Lattice operating system, mesh networks, and other hardware products to engage in cyber operations at the edge. We design and build novel solutions to deploy cyber capabilities in unconventional or difficult to reach environments Anduril Cyber is hiring a Software Engineer focused on embedded and mission software integration. Strong candidates may lean more heavily toward embedded-platform or mission/backend work, but should be comfortable collaborating across adjacent layers that connect devices, operators, and data products.

ABOUT THE JOB

Anduril Cyber is hiring an FPGA Engineer with deep experience in high-throughput FPGA/SoC digital design, precision timing, and hardware/software integration. The role is defined around the technical depth and execution patterns reflected in the hiring plan and representative resume set without assuming a fixed silicon choice this early. Design and implement high-throughput FPGA datapaths, packetization pipelines, timing-sensitive interfaces, and hardware-near acceleration blocks. Own RTL design, simulation, verification, and lab bring-up across VHDL, Verilog, or SystemVerilog-based workflows. Work closely with DSP, software, hardware, and systems engineers to turn algorithm and interface requirements into robust FPGA implementations. Drive precision timing, synchronization, and throughput closure for the selected FPGA/SoC platform and adjacent high-speed digital interfaces. Document architectures, interfaces, and verification approaches clearly enough for cross-functional integration and long-term maintainability. Support design reviews, technical trade studies, and lab debugging with a hands-on, player-coach engineering mindset. REQUIRED QUALIFICATIONS Strong experience with FPGA development on Xilinx or comparable platforms, including SoC/MPSoC-based or other high-performance digital devices relevant to SDR systems. Proficiency in VHDL, Verilog, or SystemVerilog, including simulation, timing closure, and resource/performance tradeoffs. Experience building high-speed digital interfaces and datapaths such as Ethernet-based packet movement, DMA-adjacent flows, or streaming signal pipelines. Hands-on familiarity with precision timing, synchronization, sysref/clocking concepts, and deterministic interface behavior. Experience with FPGA verification methodologies and automation, including regression-oriented testbenches and CI-backed validation. Ability to collaborate effectively with software and DSP engineers on register interfaces, control surfaces, and integration boundaries. Comfort debugging in the lab using oscilloscopes, logic analyzers, spectrum analyzers, or related instrumentation. Strong written and verbal communication skills for technical design reviews and cross-functional engineering work PREFERRED QUALIFICATIONS Experience with cocotb, GitLab CI/CD, or similar automation for FPGA verification and release confidence. Background in FFT/channelization pipelines, PSD generation, AGC-adjacent blocks, or other signal-processing-oriented FPGA implementations. Familiarity with embedded software interfaces to FPGA systems, including Linux-based control planes and hardware/software co-debug. Experience presenting architecture and implementation details in customer-facing or formal design-review settings. Track record of mentoring other engineers and improving design quality across a broader FPGA/DSP team. US Salary Range$166,000—$220,000 USDThe salary range for this role is an estimate based on a wide range of compensation factors, inclusive of base salary only. Actual salary offer may vary based on (but not limited to) work experience, education and/or training, critical skills, and/or business considerations. Highly competitive equity grants are included in the majority of full time offers; and are considered part of Anduril's total compensation package. Additionally, Anduril offers top-tier benefits for full-time employees, including: Benefits At Anduril, we invest in our people. Our comprehensive, competitive benefits package (available at little to no cost to employees) ensures you’re supported in health, recovery, and whatever comes next. For more information, Explore Our Benefits.