Silicon Packaging Engineering Manager

Job Details Intel Foundry is seeking a highly experienced IC Packaging Design Manager to lead the delivery of advanced packaging solutions within the Advanced Design and Customer Engineering (ADCE) organization. The manager will lead a team responsible for driving package design execution to ensure first‑pass success across customer programs and will act as a trusted technical partner to customers, enabling successful adoption of Intel’s advanced packaging technologies (EMIB, Foveros, chiplet architectures). This position requires technical depth and leadership across all aspects of advanced packaging design. Key Responsibilities Leadership and Management Lead and manage a group of IC Packaging Engineers, providing guidance, mentorship, and support to ensure the successful execution of projects. Oversee the planning, scheduling, and execution of package design projects, ensuring that milestones and deadlines are met. Foster a collaborative and innovative team environment, encouraging continuous learning and professional development. Lead design groups, coordinating efforts across multiple teams to achieve project goals. Technical Expertise Serve as the primary package design technical lead and guide customers through end‑to‑end package design flow. Drive the development of advanced packaging designs, ensuring compliance with industry standards and best practices. Collaborate with cross‑functional teams—including package architects, silicon and board design teams, design rule owners, electrical analysis engineers, and integration teams—to define and implement design specifications. Leverage extensive experience in advanced packaging designs to meet design KPIs. Ensure products are designed and developed with high quality standards by overseeing design processes, risk management, and compliance throughout the product design lifecycle, working closely with cross‑functional teams to identify and address potential quality issues before they arise. Project Management Develop and maintain detailed project plans, including resource allocation, risk management, and progress tracking. Coordinate with stakeholders to ensure alignment on project goals, deliverables, and timelines. Conduct regular project reviews and provide status updates to senior management. Innovation and Improvement Identify and implement process improvements to enhance the efficiency and quality of package designs and development. Stay current with industry trends and emerging technologies, incorporating new methodologies and tools into the design process. Drive innovation in product design, exploring new approaches and techniques to achieve competitive advantages. Qualifications Minimum Qualifications Bachelor’s degree in Electrical Engineering or STEM related field with 9+ years of relevant experience OR Master’s degree with 6+ years OR PhD with 4+ years. Relevant experience includes: Experience in IC Package, chiplet/SOC design, or heterogenous integration, with at least 3 years in a leadership role. Proven leadership or management experience, with a track record of successfully leading engineering teams and delivering complex projects within established timelines. Experience in performance, manufacturability, or yield‑aware design methodologies. Experience with design flows and methodologies (physical design, analysis, verification). Experience working with IC Packaging EDA tools from Siemens and/or Cadence. Experience with packaging technologies and heterogenous integration. Preferred Qualifications Experience with IC Packaging designs for HPC/AI class of products. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Additional Information Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. Candidates should never be required to pay recruitment fees, medical examination fees, or any other charges as a condition of employment. If you are asked to pay any fees during our hiring process, please report this immediately to your recruiter. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, Arizona, Phoenix Additional Locations US, California, Santa Clara; US, Oregon, Hillsboro Benefits We offer a total compensation package that includes competitive pay, stock bonuses, and benefit programs such as health, retirement, and vacation. Work Model for this Role This role will require an on-site presence. #J-18808-Ljbffr Intel