Senior RTL Engineer - Networking ASIC for AI Infrastructure
$210k - $275kEridu Corporation
A leading technology firm is seeking experienced RTL designers to help define and implement cutting-edge Networking ASICs. Candidates should have 8-15 years of experience, strong knowledge of SystemVerilog and Verilog, and expertise in ASIC design methodologies. This role involves designing high-speed networking chips and optimizing performance metrics. The position offers a competitive salary range of $210,000 - $275,000 per year, reflecting the candidate's skills and experience while impacting AI infrastructure innovation. #J-18808-Ljbffr
Vacancy posted 18 hours ago
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