RISC-V RTL Engineer for High-Performance CPU
Tenstorrent
Tenstorrent seeks a talented CPU design engineer to iterate front-end CAD flows for a RISC-V based CPU, collaborating with DV, PD, RTL and performance teams to achieve timing, power, and area convergence. You will perform synthesis, place and route, and work with core micro-architects to optimize configurations for best PPA, while pushing physical design methodologies and tools to improve efficiency. The role is hybrid, based in Austin or Santa Clara, with learning opportunities across the CPU
#J-18808-LjbffrVacancy posted 20 hours ago
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