Design Verification Engineer
NexTech Capital
Job Description
Multiple Design Verification (DV) Opportunities - U.S. Based (Hybrid & Onsite)
\n \n \nWe are partnered with several cutting-edge semiconductor client s who are actively hiring Design Verification Engineer s across a range of domains. These roles are NOT fully remot e - each has a defined hybrid or onsite expectation, outlined below
\n \nIf you’re a DV engineer exploring your next move, chances ar e one of these aligns we ll
\n \n \nBay Area, CA – Onsite (4x/week)
\nDV Engineer – AI Native
\n• Deep experience verifying AI/ML accelerators, LLMs, TPUs, etc.
\n• 2–13 years of experience
\n \nBay Area, CA – Hybrid
\nDV Engineers – Multiple Domains
\nLooking for DV engineers with experience in one or more of the following:
\n• CPU / Processor
\n• Networking
\n• PCIe / Ethernet
\n• AI Accelerators
\n• UCIe / CXL
\n• NoC / NIC
\n• Memory Controller
\n \n \nVacancy posted 29 days ago
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