Senior Logic Design Engineer

Microsoft Silicon Cloud Hardware and Infrastructure Engineering ( SCHIE ) is the team behind Microsofts expanding Cloud Infrastructure and responsible for powering Microsofts Intelligent Cloud mission. SCHIE delivers the core infrastructure and foundational technologies for Microsofts over 200 online businesses including Bing MSN Office 365 Xbox Live Teams OneDrive and the Microsoft Azure platform globally with our server and data center infrastructure security and compliance operations globalization and manageability solutions. Our focus is on smart growth high efficiency and delivering a trusted experience to customers and partners worldwide and we are looking for engineers to help achieve that mission.

The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design development manufacturing and packaging of Microsofts state-of-the-art computer chips notably the Azure Cobalt. Our solutions provide sustainable strategic advantages to Microsoft and enable our customers to achieve more.

As Microsofts cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time in high volume with high quality and lowest cost is of paramount importance. To achieve this goal the Silicon Logic Design team is instrumental in defining and delivering operational measures of success for hardware manufacturing improving the planning process quality delivery scale and sustainability related to Microsoft cloud hardware. We are looking for experienced engineers with a dedicated passion for customer focused solutions insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure.

We are looking for a Senior Logic Design Engineer to join the team driving high-quality RTL towards Physical Design handoff with a particular emphasis on static timing analysis SDC constraints and synthesis correlation and quality.

#SCHIE #CSME

The candidate for this position will be expected and able to complete the following responsibilities:

• Design develop and maintain robust timing (SDC) constraints ensuring functional correctness hierarchical consistency and tool compatibility while enabling PPA targets.
• Leverage state of the art tools to generate constraints and perform quality assurance for PD and STA consumption.
• Collaborate and support Physical Design STA and DFT teams with collaterals from initial RTL handoff to tape out.
• Analyze and debug synthesis results to drive RTL optimization towards achieving PPA targets
• Automate tasks using scripting for efficiency
• Utilize AI for gaining efficiency within process and development
• Continue to grow your micro-architectural knowledge and contribute to unit sub-system and SOC micro-architecture
• Development and integration of various functional block RTL
• Perform design quality checks such as Timing closure Lint CDC Synthesis Low Power Intent
• Exercise the functionality of the block by writing basic tests and debug for various features at IP and SoC levels as deemed necessary.
• Delight your customers by providing high-quality functional blocks on schedule and with professional integrity
• Challenge the status quo with growth mindset.
• Mentor team members and summer interns for a growing team

Required Qualifications:

• Doctorate in Electrical Engineering Computer Engineering Computer Science or related field AND 1 year(s) technical engineering experience
• OR Masters Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 4 years technical engineering experience
• OR Bachelors Degree in Electrical Engineering Computer Engineering Computer Science or related field AND 5 years technical engineering experience
• OR equivalent experience.

Other Requirements

• Ability to meet Microsoft customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.
• This role will require access to information that is controlled for export under export control regulations potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations the EU Dual Use Regulation and/or other export control a condition of employment the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g. under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement and as a condition of employment the successful candidates citizenship will be verified with a valid passport. Lawful permanent residents refugees and asylees may verify status using other documents where applicable.

Preferred Qualifications:

• Experience in static timing analysis and logic domain including SDC/Timing Constraint generation analysis and quality assurance.
• Experience with synthesis script setup debug analysis and drive to quality targets.
• Knowledge of logic design flow including Low Power Analysis UPF RTL coding Synthesis timing constraints timing closure.
• Demonstrated expertise in Computer Architecture Digital Design IP/SoC design principles as part of SoC and/or IP development.
• Highly Proficient in Verilog/System Verilog coding constructs.
• Knowledge of front-end tools (VCLP Verilog simulators Connectivity tools low power static checkers linting)
• Demonstrated experience and knowledge of clock crossings and power/UPF in design
• Ability to write scripts using Perl Tcl Python etc.
• Familiarity with Industry standard interface protocols (ARM) is a plus.
• Familiarity with Formal Equivalence Verification and Power Analysis is a plus.
• Verbal and written communication skills.

Silicon Engineering IC4 - The typical base pay range for this role across the U.S. is USD $119800 - $234700 per year. There is a different range applicable to specific work locations within the San Francisco Bay area and New York City metropolitan area and the base pay range for this role in those locations is USD $160200 - $261000 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
position will be open for a minimum of 5 days with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age ancestry citizenship color family or medical care leave gender identity or expression genetic information immigration status marital status medical condition national origin physical or mental disability political affiliation protected veteran or military status race ethnicity religion sex (including pregnancy) sexual orientation or any other characteristic protected by applicable local laws regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process read more about requesting accommodations.

Required Experience:

IC