Mixed-Signal IC Design & DV Engineer (RTL-Tapeout)
118-WW TMG MFG OPS
118-WW TMG MFG OPS in Tucson, Arizona is seeking an engineer to join our Current Sensing IC team. You will contribute to the full IC development lifecycle, from architectural development through DV, tapeout and bring-up, with emphasis on both digital and mixed-signal domains. The ideal candidate has at least 2 years of relevant experience, strong digital logic fundamentals, and familiarity with Verilog, SystemVerilog, VHDL, and UVM environments. #J-18808-Ljbffr 118-WW TMG MFG OPS
Vacancy posted 3 days ago
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