RTL-to-GDS Physical Design Engineer for High-Speed IP

TPI Global Solutions in Santa Clara, CA is seeking a Physical Design Engineer to take RTL to GDS with synthesis, Place & Route, timing, and physical verification. The role focuses on automation-driven flows for high-speed datapath IP, floor planning, clock tree synthesis, clock gating, and signoff for large IP deliveries. Strong Verilog and EDA tool expertise preferred. Ideal candidates will have experience with ICC2, Fusion Compiler, Calibre, and PrimeTime, plus a Master's or Bachelor's degree