Sr DRAM Layout Engineer - Analog Blocks & IP
1000 Micron Technology, Inc.
1000 Micron Technology, Inc. in Boise, Idaho, is seeking a Layout Engineer to design high-quality physical layouts for DRAM technologies. This role requires experience with Cadence Virtuoso and knowledge of verification methods such as DRC and LVS. Candidates should have a strong grasp of analog layout fundamentals and experience with critical analog blocks. The position offers comprehensive benefits, including medical, dental, vision, and paid time off. #J-18808-Ljbffr 1000 Micron Technology, Inc.
Vacancy posted 3 days ago
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