Senior RTL/Logic Simulation Architect
Jobleads-US
Cadence Design Systems in California is seeking a Senior Engineer for the System Verification Group to advance the Xcelium RTL/logic simulator and tackle the growing complexity of AI and hyperscale chip designs.
You will join a geographically distributed team, lead junior engineers, and contribute to timing analysis and graph algorithms; strong C++ and SystemVerilog skills are essential, with deep expertise in RTL/logic simulation.
#J-18808-Ljbffr Jobleads-USVacancy posted 4 days ago
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