DFT Design Engineer: SoC/ASIC Test & MBIST Expert
Cadence
Cadence is seeking a SoC/ASIC Digital Design Engineer with strong DFT experience to join our team in Austin, TX. You will work on scan chain insertion, compression scan, MBIST, and ATPG, with hands-on synthesis, verification, and debugging of Verilog testbenches. Collaborate with cross-functional teams across Architecture, Design, and external customers to deliver robust DFT solutions while maintaining quality metrics and project timelines. #J-18808-Ljbffr Cadence
Vacancy posted 2 days ago
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