Hardware Engineer IV

Job Role: Hardware Engineer IV
Location: Sunnyvale, CA (Onsite)
Duration: 12 Months

Role Summary
We are seeking an experienced EE Validation Engineer to support hardware validation of next-generation smart glasses, working closely with the validation lead. In this role, your primary focus will be monitoring validation progress, reviewing CM test reports, analyzing failures, and coordinating with EE design partners to drive issues to closure. You will also guide CM engineers on measurement procedures and perform hands-on PI/SI debug when needed. While you must possess strong hands-on measurement skills, the majority of your time will be spent interpreting data, tracking issues, and ensuring problems are resolved efficiently. You will not own final validation decisions, but you are expected to be technically strong enough to flag risks, recommend actions, and keep execution on track under the lead's direction.


Responsibilities
Issue Tracking & Closure (Primary Focus ~60%)

• Review CM-generated validation reports: verify data quality, flag anomalies, confirm pass/fail criteria are correctly applied
• Analyze validation failures; determine whether issues are measurement errors, design defects, or assembly quality problems
• Coordinate with EE design partners to present data, propose root cause hypotheses, and support corrective action decisions
• Track open issues through resolution; ensure fixes are validated and closed in a timely manner
• Facilitate communication between CM, EE design, layout, and firmware teams to keep issues moving
• Maintain issue tracker and provide regular status updates to the FTE validation lead
• Monitor overall validation progress against milestones; escalate risks and blockers early

CM Guidance (~20%)

• Develop clear, repeatable test procedures (SOPs) that CM technicians can execute independently
• Train and guide CM engineers/technicians on proper measurement techniques, probe placement, fixture usage, and data collection
• Define probe points and measurement access strategy; communicate to CM with annotated layout markups
• Provide real-time technical guidance to CM when measurements yield unexpected results
• Establish clear acceptance criteria and escalation paths for CM to follow, in alignment with the FTE validation lead

Hands-On Measurement & Debug (~20%)

• Perform PI/SI measurements that require senior-level judgment (e.g., first article bring-up, intermittent failures, subtle noise sources)
• Validate CM measurement setups by performing correlation measurements
• Debug escalated issues that CM cannot resolve independently
• Develop new measurement methodologies and fixtures for novel circuits or challenging probe access
• Support prototype bring-up and characterization during build phases

Technical Knowledge Required
Power Integrity (PI)

• DC-DC converter characterization: line/load regulation, efficiency, transient response, output ripple/noise
• Power sequencing validation and timing verification against IC specifications
• Power rail stability under varying load conditions; current profiling
• Battery charging circuit validation: charge profiles, protection, thermal limits
• PDN concepts: ground bounce, decoupling strategy, voltage droop analysis

Signal Integrity (SI)

• High-speed interface measurement: MIPI CSI, SPI, I2C, I2S/PDM, USB, UART
• Signal quality assessment: rise/fall times, overshoot/undershoot, ringing, eye diagrams
• Crosstalk, reflections, and impedance discontinuities on flex/rigid-flex assemblies
• Clock signal quality and jitter characterization
• Protocol-level correlation with physical-layer signal issues

Schematic & Layout Competency

• Read and interpret multi-page schematics to understand circuit topology, power trees, and signal routing
• Review PCB layout (rigid and flex) to identify optimal probe locations and debug access points
• Assess layout for SI/PI risk: trace routing, return path continuity, impedance control, via transitions
• Provide layout feedback to design team for improved testability

Required Qualifications

• BS/MS in Electrical Engineering
• 4+ years of EE hardware validation experience with strong Client on power integrity and signal integrity
• Proven ability to analyze test data, identify root causes, and drive issues to closure with cross-functional teams
• Experience reviewing test reports for correctness, identifying gaps, and driving follow-up actions
• Ability to develop test procedures that others execute - clear technical writing, structured SOPs, annotated diagrams
• Strong schematic reading skills - trace signal paths, understand power distribution, map circuit function from schematics and datasheets
• PCB layout review experience - assess probe access, SI/PI risk, debug strategy
• Expert-level knowledge of lab instruments: high-bandwidth oscilloscopes, power rail probes, active/differential probes, current probes, spectrum analyzers
• Experience with DC-DC converter characterization and high-speed digital signal measurements
• Solid understanding of transmission line theory, impedance matching, and flex PCB signal integrity challenges
• Strong communication skills - ability to explain complex EE issues clearly to CM teams and design partners

Preferred Qualifications

• Experience working with CMs or ODMs in a validation support capacity
• Experience with wearable, mobile, or IoT hardware (space-constrained, low-power designs)
• Familiarity with RF measurement (BLE/WiFi TX power, sensitivity, antenna return loss)
• Familiarity with proto/EVT/DVT/PVT build cycles and NPI environments
• Experience with issue tracking systems and cross-functional coordination in hardware programs

Tools & Environment

• Instruments: Keysight/Tektronix oscilloscopes (≥1 GHz), power rail probes, active probes, SMUs, VNAs, protocol analyzers
• Software: scripting, schematic/layout viewers (Allegro, Altium, or equivalent), data analysis tools
• Documentation: Google Workspace, Tasks/JIRA for issue tracking
• Collaboration: Daily interaction with validation lead, CM engineers (remote and on-site), EE design team, and FW