Power-Management & Clocking Architect for RISC-V Cores
SiFive, Inc.
A leading technology firm in Santa Clara is seeking a passionate Power-Management/Reset/Clock Micro-Architect and RTL Design Engineer to design innovative CPU and interconnect IP based on RISC-V. The role involves power management architecture, clocking solutions, and collaboration with various teams to optimize designs. Candidates should have 3+ years of experience, proficiency in Verilog/SystemVerilog, and a degree in a related field. The company offers a comprehensive benefits package and a collaborative work environment. #J-18808-Ljbffr SiFive, Inc.
Vacancy posted 2 days ago
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