SoC Memory Subsystem Architect

Do you want to be part of the AI revolution? Do you want to think out of the box, thrive on challenges in the AI industry, and have the desire to solve them? Do you want to work with a world‑class team to explore the fast‑growing AI hardware opportunities and impact on the AI industry? We’re looking forward to having you join us to collaborate, contribute, and revolutionize AI silicon and system. Description We are looking for a world‑class Memory Subsystem Architect to join our SoC team at Baidu’s Sunnyvale office. The successful candidate will be a motivated self‑starter who will thrive in this highly technical environment. As a Memory Subsystem Architect you will provide technical leadership through all phases of Baidu’s AI SoC development, focusing primarily on unified memory space architecture design for Baidu’s AI accelerator SoC. Your goal is to build a unified memory space for thousands of accelerators from the user’s perspective. Responsibilities include: Developing architecture and micro‑architecture to improve the state‑of‑the‑art AI SoC memory system. Exploring and evaluating architectural design choices in SoC fabrics, system caches, system coherency, and MMUs. Working with software and SoC design teams to define architecture and build a unified memory space system across distributed AI training systems. Collaborating with hardware design, verification, emulation, and validation teams to build and test hardware architecture, performance, and functionality. Participating in performance simulation of features to improve memory subsystem efficiency, analyzing benchmarks, application workloads, and performance simulation results to identify micro‑architecture optimization opportunities. Debugging performance and functional issues with high‑level models, RTL simulation, and silicon. Qualifications 10+ years of experience in silicon architecture or IP design, mainly focusing on memory subsystem. Strong understanding of distributed AI training system requirements on SoC memory subsystem. Demonstrated experience in HW digital design and understanding of CPU/HW accelerators and/or peripheral design. Familiarity with software and operating system practices and requirements on memory system. Experience in system performance analysis and debugging in pre‑ and/or post‑silicon environments. Solid background in system interconnect, system MMUs, caches, and memory technologies (e.g., HBM, GDDR, DDR, LPDDR4/5). Experience with data analysis using Excel, Perl, Python, etc. Master or Ph.D. in Electrical or Computer Engineering. Excellent communication skills in both English and Chinese. Culture Fit Mission alignment: If you want to be part of a team achieving this great mission, we will provide you the best possible platform. Self‑directed: We work best with people who are driven, motivated, and aspire to greatness. Hungry to learn: We are eager to see you learn new skills and grow. Team orientation: We work in small, fast‑moving teams. We look out for each other and pursue big goals together. As set forth in Baidu USA’s Equal Employment Opportunity policy, we do not discriminate on the basis of any protected group status under any applicable law. #J-18808-Ljbffr Baidu USA