SystemC Modelling Engineer

Systemc Modelling Engineer

Location: Redmond, WA (Remote)

Must Have Skills:

SystemC Modelling Engineer Skill 1 – 8+ Yrs of Exp in SystemC & TLM

Skill 2 – 4+ Yrs of Exp in Hardware Description Languages (HDLs): VHDL or Verilog

Skill 3 – 5+ Yrs of Exp in Python

Required Skills:

• SystemC & TLM (Transaction Level Modeling)
• C++ (Proficient level, including object-oriented design principles)
• Hardware Description Languages (HDLs): VHDL or Verilog (Understanding and ability to interface with)
• Simulation Tools (e.g., Cadence Incisive, Synopsys VCS, Mentor Graphics QuestaSim)
• Debugging Tools (e.g., GDB, DVE)
• Scripting Languages (Python, Perl, or similar)
• Version Control Systems (Git)
• Embedded Systems Architecture (Understanding of processor architectures, memory hierarchies, and bus protocols)
• Communication (Excellent written and verbal communication skills)
• Problem-Solving (Strong analytical and problem-solving abilities)
• Team Collaboration (Ability to work effectively in a team environment)
• Defining transaction level models of non-memory mapped interfaces (I2C, SPI, USB, CAN, Ethernet etc)
• Porting the embedded operating system (Linux, VXWorks, Android ) on the virtual prototype, developing the device drivers etc.
• Verification of models at IP & SoC level.
• Develop regress able self-checking test suites using C/ARM assembly.
• Develop System Level Flows and Methodologies using virtual prototypes