R&D Engineering, Principal Engineer- 15024

We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from self-driving cars to learning machines. We lead in chip design, verification, and IP integration, empowering the creation of high-performance silicon chips and software content. Join us to transform the future through continuous technological innovation. In this role, you will work on the design, development, and refinement of Multi-Gbps NRZ & PAM4 SERDES IP. You will be part of a fast-growing analog and mixed signal R&D team developing high speed (>200Gbps) analog integrated circuits in the latest FinFET process nodes. Working from SerDes standards to block specifications, you quickly identify potential circuit architectures and successful design strategies. You will work with a cross functional design team of analog and digital designers from a wide variety of backgrounds. Our environment is best in class with a full suite of IC design tools supplemented by custom, in-house tools supported by an experienced software/CAD team. You Are: You are an accomplished analog design engineer with a passion for pushing the boundaries of high-speed connectivity. You thrive on solving complex technical challenges and are energized by collaborating with cross‑functional teams to deliver best‑in‑class silicon solutions. Your expertise in SerDes and high-speed analog circuit design is complemented by your hands‑on experience in developing, verifying, and optimizing circuits for high performance, low power, and minimal area. You are deeply familiar with the intricacies of CMOS design, and have a proven track record of successfully taping out silicon‑proven designs for modern communication interfaces. You are detail‑oriented, with a rigorous approach to design documentation and verification, and you communicate complex technical concepts with clarity to both peers and customers. You are comfortable navigating the entire design flow, from architectural review and specification through layout, simulation, and silicon validation. Above all, you are motivated by the impact your work has on the industry and on the innovative products that shape the world. What You’ll Be Doing: Ownership of Analog Macro level design Tracking and reviewing the work of sub-block owners Review SerDes standards and architecture documents to develop analog specifications Identify and refine circuit implementations to achieve optimal power, area and performance targets. Propose design and verification strategies that efficiently use simulator features to ensure highest quality design. Oversee physical layout to minimize the effect of parasitics, device stress, and process variation. Collaborate with digital RTL engineers on the development of calibration, adaptation and control algorithms for analog circuits. Present simulation data for peer and customer review. Mentor and review the progress of junior engineers. Document design features and test plans. Consult on the electrical characterization of your circuit within the SerDes IP product. What You’ll Need: Advanced degree with 4+ years of SerDes/High-Speed analog design experience. In-depth familiarity with transistor level circuit design - sound CMOS design fundamentals. Silicon‑proven experience implementing circuits for the TX, RX and Clock paths within a SerDes. Experience in leading a small team of designers collaborating on building blocks of a Macro level design. Detailed design experience with several of the following SerDes sub‑circuits: receive equalizers data samplers voltage/current‑mode drivers serializers deserializers voltage‑controlled oscillator phase interpolator delay‑locked loop phase‑locked loop bandgap reference ADC DAC Experience optimizing FinFET CMOS layout to minimize the effect of parasitic resistance and capacitance, and to reduce the effects of local device mismatch and proximity effects. Awareness of ESD issues (i.e. circuit techniques, layout) and design for reliability (i.e. electro‑migration, IR, aging, etc.). Experience with EDA tools for schematic entry, physical layout, and design verification. Knowledge of SPICE simulators and simulation methods. Knowledgeable in Verilog‑A for analog behavioral modeling and simulation‑control/data‑capture. Experience with TCL, Perl, C, Python, MATLAB. Who You Are: Innovative, analytical, and detail‑oriented problem solver. Effective communicator with strong presentation and documentation skills. Collaborative team player who thrives in multidisciplinary environments. Motivated mentor and coach for junior engineers. Adaptable to changing project requirements and new technologies. Self‑driven and committed to continuous professional development. The Team You’ll Be A Part Of: You will join a high-impact analog/mixed‑signal design team renowned for delivering state‑of‑the‑art SerDes IP solutions. The team’s focus is on innovation, quality, and collaboration, working closely with digital design, layout, verification, and product engineering teams. Together, you will tackle complex design challenges, develop next‑generation connectivity IP, and support customers worldwide in deploying industry‑leading silicon solutions. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. #J-18808-Ljbffr Synopsys, Inc.