Principal Physical Design Engineering Lead ($400-500k) (Irvine)

Principal ASIC Engineering Lead (Physical Design OR STA)Up to $230k base, + 30% bonus plus around $800k-$1.2m in stocks which vests over 4 years. Total first year realistic income $450-500kLocations: San Jose, CA, Irvine, CA or Fort Collins, COIntroductionAre you a seasoned Engineer who excels at guiding complex semiconductor programs across areas such as physical design, STA, DFT, and packaging and a passion for working on bleeding-edge AI and high-performance silicon? Have you delivered enough chips to recognize hidden issues in EDA reports before they impact schedules, and can you clearly explain both the technical root cause and the long term solution? Do you enjoy deep technical discussions with engineering teams while also providing clear, high level summaries to management?If this sounds like you, and you want to work on advanced compute and infrastructure silicon, this role may be an excellent match.Top Reasons to Work With UsSupport customers building cutting edge ASICs in AI, HPC, networking, and storageCollaborate with highly experienced cross functional engineering and technology teamsInfluence the development of next generation semiconductor technologiesTake ownership of customer success from initial engagement through productionShape design methodologies, best practices, and implementation strategiesBe part of a supportive, collaborative environment that values technical leadershipThe Role / ResponsibilitiesAs a senior technical leader, (NOTE: prior leadership experience NOT required) you will guide customer ASIC programs and ensure successful delivery of highly complex designs. (Approximately 80% hands on, 20% technical leadership). Your responsibilities will include:Leading end to end customer ASIC programs: RFQs, technology planning, IP integration, design, test, packaging, fabrication, bring up, and productionAdvising customer teams on EDA best practices, design flows, and methodologies, including hosting Q&A sessions with technical expertsIdentifying risks related to quality, schedule, or dependencies and coordinating mitigation plans with internal and external teamsRunning physical design validation flows to ensure incoming customer netlists meet strict tape out quality requirementsStaying up to date on new technologies, IP developments, and application trendsWorking closely with marketing, sales, legal, and compliance teams on program related discussionsCollaborating with and supporting other engineering teams as needed
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tr th {}Essential SkillsMultiple tape outs at advanced process nodesAbility to analyze PPA tradeoffs across library components, architectures, and implementation strategiesStrong understanding of low power design techniques and power managementHands on experience in physical design or STA, along with EDA tools and flows covering physical design, logic simulation, test, and packagingProgramming or scripting experienceExcellent communication skillsBonus Points ForExposure to SERDES communication protocolsExperience in logic design, chip architecture, microarchitecture, Verilog RTL development, front end verification, DRC, and logic synthesisKnowledge of DFT methods including scan, memory BIST, and repairBenefitsHealth, dental, and vision insuranceLife and disability insurance FSA and HSA401k with matchESPPGenerous PTOAnnual bonus from 15-30% (depending on your level)VERY generous stocks!