Verification Engineer

To ensure the functionality and quality of complex digital designs, the full-time remote Verification Engineer will develop and maintain RTL verification environments, execute coverage-driven verification plans, and collaborate closely with RTL design engineers. Key Responsibilities: Develop, implement, and maintain RTL verification environments using UVM or equivalent methodologies Create and execute coverage-driven verification plans aligned with design specifications Analyze simulation results and debug complex verification and design issues in collaboration with RTL design engineers Required Qualifications: Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field 7+ years of experience in digital design verification Strong hands-on experience with UVM-based or similar verification methodologies Proficiency in SystemVerilog, UVM, and Python Experience with industry-standard EDA tools (e.g., Synopsys VCS, Siemens/Mentor Questa, Cadence Xcelium)