Senior DDR5/6 Analog Lead & Architect
Renesas
Renesas is looking for a Senior Analog Engineering Manager to guide the architecture, design, and implementation of DDR5 PHYs while contributing to DDR6-ready architectures. This role involves technical oversight of critical analog and mixed-signal blocks and leading engineering teams focused on high-speed memory interfaces. The ideal candidate will have 12+ years of experience in analog/mixed-signal IC design, a strong expertise in high-speed IO design, and a proven track record of delivering DD PHYs. This position also requires strong leadership skills and the ability to foster a culture of innovation and execution excellence. #J-18808-Ljbffr Renesas
Vacancy posted 1 day ago
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