Senior SoC RTL Design Engineer
Synopsys Inc
Synopsys Inc. in Gilbert, AZ is seeking an RTL engineer to turn RTL specifications into robust Verilog/SystemVerilog designs for block‑level architectures, including state machines, pipelines, FIFOs, and memory controllers. You will ensure clean synthesis and meet timing goals across the ASIC/FPGA flow. You will collaborate with verification, DFT, and physical design teams globally, write automation scripts (Python/Tcl), and participate in design reviews to communicate tradeoffs and decisions. #J-18808-Ljbffr Synopsys Inc
Vacancy posted 3 days ago
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