Cellular ASIC Design Engineer

Description As a Cellular ASIC Design Engineer, you'll develop and optimize design and implementation methodology for integrated circuits across multiple focus areas including area efficiency, power optimization, and design technology co-optimization. You'll design innovative products at the block/IP-level and system-level in advanced process technologies (3nm, 2nm and beyond). Your primary responsibilities will involve developing best‑in‑methodologies for optimizing Power, Performance, Area, and Cost efficiency metrics through various approaches: Design Flow & Methodology Development – Establish design guidelines, methodologies, and standards for synthesis, place‑and‑route, timing closure, and signoff processes; develop and optimize EDA tool flows including synthesis tools (DC/DCT/DCG/Genus/Oasis), P&R tools (ICC2/Fusion/Innovus/Aprisa), and signoff tools (PT/PT‑SI/Tempus); drive timing convergence process improvements across design teams to enhance design PPA and yield; create and maintain comprehensive design flows, scripts, and automation tools to improve design productivity and reduce turnaround time. Physical Design & Implementation – Identify utilization bottlenecks in physical design and develop architectural, design, and implementation‑level solutions to improve utilizations; work with physical design teams on timing closure, collaborating with CAD teams, IP teams and Design Technology teams for flow scripts/tools development and validation; understand RTL to GDS digital flow and provide hands‑on contribution for timing signoff of complex SOCs. Analysis & Validation – Perform design technology co‑optimization analysis, including optimal operating point analysis for performance/power curves and identification of scaling trends and bottlenecks in advanced technology nodes; conduct Spice simulations (Hspice/Finesim/AFS/Spectre/Infinisim) for PVT corners validation and STA vs spice correlation; perform timing package validation across advanced process technologies and timing signoff specification development; conduct in‑depth analysis of design databases and silicon validation data to identify critical issues and improve overall design metrics; understand intricate timing paths (digital, analog, mixed signal) and timing constraints, providing solutions as required. Power & Performance Optimization – Develop and implement voltage scaling and power optimization methodologies including clock gating, power gating, and dynamic voltage/frequency scaling techniques; use power analysis tools (RedHawk/SeaHawk/Voltus) for comprehensive power signoff and optimization; facilitate and drive STA methodology improvements using industry‑leading timing tools and ECO methodologies. Multi‑Functional Collaboration – Collaborate closely with technology and IP teams to enhance efficiency through custom and semi‑custom IP development; work closely with process technology, front‑end design, physical implementation, CAD, and multi‑functional teams to develop innovative solutions; support advanced process technology bring‑up from PDK to VLSI design production; drive DFT (Design for Test) methodology improvements including scan insertion, ATPG, and built‑in self‑test strategies. Technical Leadership – Stay ahead of industry trends and emerging technologies to continuously improve design methodologies; apply strong programming skills (Python, Perl, TCL, Unix shell, C/C++) for methodology automation and enhancement; apply ML modeling experience for advanced design optimization and predictive analysis. Minimum Qualifications BS and a minimum of 20 years relevant industry experience. VLSI background with hands‑on experience in RTL to GDSII flows. Expert in doing Power, Performance, Area and Cost optimizations for SoCs. Experience with SoC power flows & Vmin optimization. Experience with Design Technology Co‑optimization, identifying and solving scaling bottlenecks in new technology nodes. Expert in rapid prototyping and scripting of methodologies and test chip block implementation. Preferred Qualifications Experience with Physical Design challenges, proficiency with synthesis, place and route tools, and implementation exploration. Experience with Metal stack optimizations. Experience performing Early Tech node analysis to identify implementation bottlenecks. Design Technology Co‑optimization expertise. Strong analytical skills and ability to identify and communicate high return on investment opportunities. Ability to apply data science and ML analytics for Frontend and Backend databases, as well as post‑silicon data, to identify trends & patterns and fine‑tune implementation methodologies. Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. Base pay for this role is between $201,300 and $367,400, and your base pay will depend on your skills, qualifications, experience, and location. Apple employees also receive benefits including comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and reimbursement for certain educational expenses (including tuition). Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program. Apple is an equal‑opportunity employer that is committed to inclusion and diversity. We seek to promote equal opportunity for all applicants without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, disability, Veteran status, or other legally protected characteristics. Learn more about your EEO rights as an applicant. #J-18808-Ljbffr Apple Inc.