Analog Layout Engineer

We are seeking an experienced Analog Layout Engineer for a contract role in Tucson, AZ, to support high-precision analog IC layout using specific flows and process nodes. Key Responsibilities Perform full-custom analog layout design for analog/mixed-signal products. Utilize proprietary design flows and methodologies on LBC9 (130-nm BCD/analog process) and HPA9 (high-performance analog node) technologies. Execute high-quality layouts using industry-standard tools (primarily Cadence Virtuoso suite for layout/schematic integration, Calibre for DRC/LVS/PEX verification, and related toolchain). Ensure best practices for matching, symmetry, parasitics, EM/IR, ESD, and density in analog designs. Required Qualifications 5–10 years of hands‑on analog layout experience in semiconductor design. Proven expertise with LBC9 and HPA9 process nodes. Proficiency in analog layout tools, including Cadence Virtuoso suite and Calibre (or equivalent verification tools). Seniority Level Mid‑Senior level Employment Type Contract Job Function Design and Engineering Industries Semiconductor Manufacturing Benefits Medical insurance Vision insurance 401(k) #J-18808-Ljbffr ALKU