R&D Engineering, Scientist

Open to: US-wide (remote or hybrid), with a preference for on‑site collaboration You Are: You are a recognized technical leader in high‑speed memory interface design, with deep expertise spanning architecture, circuits, and system‑level integration. You operate at a mastery level and are known for your ability to guide teams through complex technical challenges while influencing direction through credibility and trust rather than authority alone. You bring extensive experience in many of DDR, LPDDR, HBM, die‑to‑die and SerDes interfaces, with a strong foundation in signal integrity, power integrity, and high‑speed I/O design. You are comfortable working from early pathfinding and architecture definition through to productization, and you understand how to translate market needs and customer requirements into scalable, high‑performance PHY solutions. You are naturally seen as a leader—someone others turn to for direction, clarity, and confidence. You build trust quickly, elevate those around you, and create an environment where teams can execute with autonomy and accountability. Whether or not you have formal direct reports, your impact is measured by how teams align behind you and deliver. You thrive in a fast‑paced, innovation‑driven environment and are motivated by solving hard problems that push the boundaries of performance, speed, and efficiency. What You’ll Be Doing: Leading architecture and pathfinding activities for next‑generation Memory PHY solutions (DDR, HBM, LPDDR, D2D, SerDes) Driving development of advanced circuit solutions for high‑speed interfaces, including I/O design, link design, and signal/power integrity optimization Translating customer requirements and industry trends into scalable PHY architectures and product definitions Guiding and influencing global engineering teams (architecture, design, verification) to deliver best‑in‑class IP solutions Providing technical leadership across the organization, mentoring engineers and strengthening overall capability in advanced circuits and PHY design Partnering with senior leadership to implement strategic goals with significant impact on business and product direction Engaging with key customers and industry stakeholders to shape roadmap and maintain Synopsys’ leadership in Memory IP Driving innovation in performance, speed scaling, and design methodologies for next‑generation interfaces The Impact You Will Have: Define and influence the future of Synopsys Memory PHY architecture across DDR and HBM portfolios Enable next‑generation AI, HPC, and data center systems through leading‑edge interface technologies Elevate the technical capability of the organization through mentorship, coaching, and leadership by example Drive alignment across teams and functions, ensuring successful execution of complex, high‑impact programs Position Synopsys as a continued leader in high‑speed interface IP through innovation and customer engagement Build trust and confidence across the organization as a go‑to technical authority What You’ll Need: 15–20+ years of experience in high‑speed interface or memory PHY design (or equivalent depth of expertise) Proven experience with DDR, LPDDR, HBM, and/or die‑to‑die / SerDes technologies Strong background in: PHY architecture and pathfinding High‑speed I/O design and link design Signal integrity and power integrity Advanced circuit design for high‑performance interfaces Track record of delivering complex products from concept through silicon Demonstrated ability to influence large, cross‑functional teams without formal authority Experience working with customers and translating system requirements into product solutions PhD or equivalent experience in Electrical Engineering or related field preferred Who You Are: A trusted technical leader who inspires confidence and alignment A strong communicator who simplifies complex ideas and drives decisions A strategic thinker who connects technology, customer needs, and business goals A mentor and capability builder, focused on growing talent and teams Adaptable and open‑minded — able to pivot and prioritize the best ideas, regardless of origin Results‑driven, with a strong sense of ownership and accountability We Are: At Synopsys, we drive the innovations that shape the way we live and connect. Our technology is central to the Era of Pervasive Intelligence, from AI systems to high‑performance computing. We lead in chip design, verification, and IP integration, enabling the world’s most advanced silicon solutions. The Team You’ll Be A Part Of: You will be part of the IP Group (IPG), focused on defining and delivering industry‑leading Memory PHY solutions, including DDR and HBM PHY architectures. The team owns the full lifecycle of PHY development — from early architecture and pathfinding to circuit innovation and product delivery. We closely engage with customers to understand their evolving needs and translate them into high‑performance, scalable solutions. Our work involves continuous advancement in circuit techniques and interface speeds to stay ahead of industry demands. This is a highly technical, globally distributed team that values innovation, ownership, and strong leadership presence. Rewards and Benefits: We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non‑monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process. At Synopsys, we want talented people of every background to feel valued and supported to do their best work. Synopsys considers all applicants for employment without regard to race, color, religion, national origin, gender, sexual orientation, age, military veteran status, or disability. In addition to the base salary, this role may be eligible for an annual bonus, equity, and other discretionary bonuses. Synopsys offers comprehensive health, wellness, and financial benefits as part of a competitive total rewards package. The actual compensation offered will be based on a number of job‑related factors, including location, skills, experience, and education. Your recruiter can share more specific details on the total rewards package upon request. The base salary range for this role is across the U.S. #J-18808-Ljbffr Synopsys