Lead High-Speed Analog Layout Architect
Celero Communications, Inc.
Celero Communications, Inc. is seeking a Principal High-Speed Analog Layout Design Engineer in San Jose, CA to drive layout of analog/mixed-signal IP blocks for state-of-the-art optical communication systems. You will lead floor planning, collaborate with schematic designers, mentor junior engineers, and ensure first-pass silicon success through rigorous LVS/DRC/PERC checks and advanced layout techniques. #J-18808-Ljbffr Celero Communications, Inc.
Vacancy posted 4 days ago
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