Substrate Packaging Defect Metro Tool Owner

Job Details: Job Description: We are seeking a motivated and skilled engineer to join our SPTD Yield team as a Defect Metrology Engineer. In this role, you will help drive innovation in EMIB‑T, glass core, EMIB scaling, and panel‑level packaging technologies for substrate as well as assembly test mfg (ATM) factories for Intel's IPG and IFS customers. Our goal is to be the supplier of choice for advanced, cost‑effective substrate packaging by developing leading‑edge systems, process capabilities, and inspection technologies to achieve top yields. Join us on our mission to make Intel a great workplace and industry leader. Responsibilities: Use defect inspection tools to detect and resolve process issues, collaborating with defect reduction, process integration, and module teams to improve yield. Apply real‑time data analysis, reporting, and DOE summaries to guide improvements and decision‑making. Maintain flexibility and adaptability to support the evolving demands in Yield space, responding to new challenges and requirements as they arise. Direct next‑generation tool installation, reaching major milestones‑purchase‑spec development, source inspection, design, pre‑fac, Safety level approval, Supplier qual, Intel qual, etc., by collaborating with diverse stakeholders. Demonstrate the ability to manage work independently, proactively identifying and resolving issues with minimal supervision, and providing leadership in defect metrology and Yield enhancement initiatives. Work with factory teams and module partners to maintain WIP velocity targets in your area. Develop and roll out procedures and equipment setups for defect metrology tools to ensure they meet quality goals. Set up data flows for new tools by connecting them to automation and yield analysis systems, guaranteeing smooth performance and reliable data. Create and outline equipment roadmaps that support capabilities matching program requirements for new substrate technologies. Collaborate with equipment suppliers and Supply chain partners to maintain current toolsets and enhance features, such as software and hardware upgrades, to satisfy Substrate packaging program objectives. Present critical tool and system capabilities developed to meet program deliverables to APTM leadership, showcasing both defect metrology and micro‑contamination expertise, and demonstrating a strong capacity for independent leadership, adaptability, and proactive problem‑solving in a fast‑paced, evolving environment. Performs descriptive statistical analysis, develops visualizations, applications, dashboards, or presentations and communicates insights in a clear and effective way to help the organization with better decision‑making. Organizes, interprets and structures insights from data, detects data anomalies and makes corrections. Qualifications: Minimum Qualifications: Must possess a bachelor's degree in electrical engineering, Chemical Engineering, Optical Engineering, Materials Science, Physics or related field of study and 3 years of semi‑conductor experience, OR Master's degree in electrical engineering, Chemical Engineering, Optical Engineering, Materials Science, Physics or related field of study and 2 years of Semi‑Conductor experience, OR PhD Degree in Electrical Engineering, Chemical Engineering, Optical Engineering, Materials Science, Physics or related field of study and 1+ years of Semi‑Conductor experience Previous experience in micro‑contamination management within a semiconductor manufacturing setting Experience as a Yield Analyst OR Defect reduction owner Or with Defect metrology tool ownership Strong programming skills in Python. Preferred Qualifications: Knowledge of statistics and experimental design and the skills to apply that knowledge tool qualification, and process development. Demonstrated understanding of semiconductor process flows and/or defect metrology assessment based on process requirements. Requirements listed would be obtained through a combination of industry‑related job experience, internship experience, and schoolwork/classes/research. Job Type: Experienced Hire Shift: Shift 1 (United States of America) Primary Location: US, Arizona, Phoenix Additional Locations: Posting Statement: All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, s #J-18808-Ljbffr Intel