Principal Advanced IC Packaging Engineer

Piper Companies is seeking a Principal Advanced IC Packaging Engineer who will develop and refine Chip-on-Wafer-on-Substrate technology for a for an up and coming AI network platform company focused on AI and datacenter technology. The Advanced IC Packaging engineer will be onsite 5 days a week in Saratoga, CA .

Requirements for the Principal Advanced IC Packaging Engineer include:

- Innovate and enhance CoWoS packaging processes to boost chip performance, power efficiency, and reliability.

- Collaborate with design, test, and manufacturing teams to ensure flawless chip-package integration.

- Lead failure analysis and drive yield improvements across packaging processes.

- Ensure CoWoS packaging meets all thermal, mechanical, and electrical performance standards.

- Support new product introduction (NPI) from initial prototyping to high-volume manufacturing.

- Partner with foundry and OSAT partners (e.g., TSMC, ASE, Amkor, SPIL) on process qualification and production ramp-up.

Qualifications for the Principal Advanced IC Packaging Engineer include:

- 15 years of hands-on experience in advanced semiconductor packaging and interconnect processes.

- Proven expertise in CoWoS / FOCoS (highly preferred), or FOWLP; familiarity with EMIB, InFO, and advanced 2.5D/3D integration technologies is a plus.

- Strong knowledge of thermal management, reliability testing, and signal/power integrity challenges.

- Excellent analytical and problem-solving skills with a proactive and collaborative mindset.

- Experience working with TSMC and leading OSATs.

- Previous experience working with Module integration technologies and methodologies

- Proficiency in Mandarin and English is preferred.

- Bachelor's or Master's degree in Electrical Engineering, Materials Science, Mechanical Engineering, or a related field.

Compensation for the Principal Advanced IC Packaging Engineer includes:

- Salary range: $210,000 - $300,000

- Comprehensive benefit package: Medical, Dental, Vision, 401k match plus PTO, Sick leave as required by law, and Paid Holidays

Keywords: principal packaging engineer, packaging, CoWoS, CoWoS packaging, semiconductor packaging, semiconductor, Chip-on-Wafer-on-Substrate, IC package development, IC packaging, chip performance, power efficiency, reliability, failure analysis, high-performance packaging, new product introduction, TSMC, ASE, FoCoS, 2.5D/3D integration, datacenter, remote, onsite

#LI-BH1

#LI-ONSITE

This job opens for applications on 5/29/2026. Applications for this job will be accepted for at least 30 days from the posting date.