Quantum Systems Digital Design Engineer II

Microsoft is the worlds center of expertise on topological quantum computing. We are building a scaled faulttolerantquantum computer grounded in topological qubits and integratedendtoendwith the Azure Quantum software stack.

As a Quantum Systems Digital Design Engineer II youllcollaborate closely with quantum physicists systems software RF/EE and manufacturing/production to definedesign and deliver FPGAbased ultralowlatency digital subsystems that sit at the heart of our topological quantum enginespanning readout classification errordecoder acceleration roomtemperature frontends for cryogenic control highspeed interconnects and precision clocking networks. Your work will directly impact logicalqubit stability throughput and system scale.

At Microsoft Quantum we aim to empower science and scientists to solve the worlds biggest problems by realizing advanced computing platforms at the intersection of high-performance computing artificial intelligence and quantum information technology. Microsoft Quantum will change the world of computing and help solve some of humankinds currently unsolvable problems. For more information about our team visit & implement RTLfor streaminglow latencypipelines (e.g. readout classifiers syndrome aggregation and QEC decoder kernels) in Verilog/SystemVerilog including resource/performancetrade offsand power/thermal considerations.

• Design and implementhigh speedinterconnectsbetween subsystems (AXI4/AXI Stream JESD204(B/C) Aurora Ethernet/UDP PCIe) including SERDES configuration linkbring up and throughput/latency tuning.

• Design robust clocking & CDCstrategies (MMCM/PLL trees jitter budgetsmulti domaintiming closure async FIFOs metastability analysis) for deterministic performance.

• Co designhardware/firmware/software boundaries(register maps DMA interrupt models driver interfaces) with control/readout software and instrument teams; contribute tosystem leveldesign reviews.

• Verification and validation:develop simulation andconstrained randomtests (SV/UVM or equivalent) buildon boarddiagnostics (ILA/ChipScope) and execute labbring upwith scopes VNAs LA/SC and RF instruments.

• Tool flow & CI:own synthesis/implementation (Vivado/Vitis or Quartus/Prime) timingsign off and reproducible scripted builds (Tcl/Python) integrated with Git/Azure DevOps CI/CD.

• Quality & documentation:produce clear design docsinterfacespecs andbring upguides;participatein rigorous code/design reviews andpost silicon/post fabricationretros.

• Embody our Culture and Values

Required

• Masters Degree in Physics Electrical/Computer Engineering or related field AND 1 years experience in industry or in a research and development environment

  • OR Bachelors Degree in PhysicsElectrical/ComputerEngineering or related field AND 2 years experience in industry or in a research and development environment

  • OR equivalent experience.

• This position requires verification of citizenship or other protected status to meet legal requirements of the role. If the role requires US citizenship as indicated in the job description a valid US passport must be provided to verify your citizenship. If the role requires US Person status as indicated in the job description US citizens must provide a valid US passport for verification while lawful permanent residents refugees and asylees may complete this verification using green cards or other status documents as applicable.

Additionalor Preferred Qualifications

• 3 years building production FPGA designs inVerilog/SystemVerilog(or VHDL) including synthesis P&R and static timing analysis on Xilinx/AMD (UltraScale/Versal/RFSoC) and/or Intel platforms.

• Proven delivery oflowlatency streamingdatapaths(DSP filtering classification ordecoderlikepipelines) with tight timing closure at high clocks.

• HandsonwithhighspeedI/Oandprotocols: AXI4/AXIS JESD204(B/C) AuroramultigigSERDES; competent in linkbringup eye margins and error budget analysis.

• Proficiencyinclocking/CDCfundamentals and experience withmulticlockmultiresetsystems.

• Verificationskills (simulation assertionstestbenches;UVMa plus) andlab debugusing ILA/ChipScope scopes LA and RF test gear.

• Familiarity withRFSoCarchitectures (data converters JESD links) and/orheterogeneouscoprocessingwith CPUs/GPUs.

• Comfort working acrossHW/SW boundaries(DMA perf tuning driversgRPC/REST control surfaces telemetry/observability)and withscientific instrumentation.

• Experience acceleratingdecoders(e.g. graph/unionfind/MWPMstyleorLDPCclasstechniques) streaming inference/classification or similarrealtimealgorithms.

• Exposure toHLS(C/C/HLS kernels) and mixed HLS/RTL systems; formal verification.

• Background insignal processing/controlor quantum control/readout concepts (nice to have; curiosity and fast learning are more important).

• Experience withWindows & Linux VS Code Git/GitHub Azure DevOps CI/CD; scripted builds (Tcl/Python); design docs code reviews comprehensive testing are part of our quality bar.

Other Requirements

• Abilityto meet Microsoftcustomerand/or government security screening requirements arerequiredfor this role. These requirements include but are not limited to the following specialized security screenings:

• Microsoft Cloud Background Check: This position will berequiredto pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter.

• Citizenship & Citizenship Verification: This role will require access to information that is controlled for export under export control regulations potentially under the U.S. International Traffic in Arms Regulations (ITAR) or Export Administration Regulations (EAR) the EU Dual Use Regulation and/or other export control regulations. As a condition of employment the successful candidate will be required to provide either proof of their country of citizenship or proof of their U.S. permanent residency or other protected status (e.g. under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legalrequirement and as a condition of employment the successful candidates citizenship will be verified with a valid passport. Lawful permanent residents refugees and asylees may verify status using other documents where applicable.

• Ability to work in an AI first environment using modern AI tools to accelerate discovery through hardware development.

• Familiarity with designing and building AI agents/copilots that assist with experiment setup log triage measurement report generation protocol templating and knowledge retrieval.

Quantum Engineering IC3 - The typical base pay range for this role across the U.S. is USD $102100 - $202200 per year. There is a different range applicable to specific work locations within the San Francisco Bay area and New York City metropolitan area and the base pay range for this role in those locations is USD $133800 - $219200 per year.

Certain roles may be eligible for benefits and other compensation. Find additional benefits and pay information here:
position will be open for a minimum of 5 days with applications accepted on an ongoing basis until the position is filled.

Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age ancestry citizenship color family or medical care leave gender identity or expression genetic information immigration status marital status medical condition national origin physical or mental disability political affiliation protected veteran or military status race ethnicity religion sex (including pregnancy) sexual orientation or any other characteristic protected by applicable local laws regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process read more about requesting accommodations.

Required Experience:

IC