Advanced Defect Modeling and Testing (Technical Manager) (7101)

Overview We are seeking an experienced engineer to join our team researching advanced defect modeling, testing, screening, and analysis for next-generation semiconductor processes and 3D packaging technologies. The role is strategically critical for TSMC and represents a multi-year journey to pioneer new approaches to defect modeling in advanced packaging. Defect modeling in this space is still an emerging discipline with global leaders actively defining standards. This position provides an opportunity to keep TSMC at the forefront of innovation and shape the methodologies that will guide the industry. The successful candidate will develop methodologies and tools to model and simulate defects, assess their impact on performance, optimize testing strategies, and innovate beyond current testing instruments. This engineer will collaborate across design, process, test, and reliability functions to ensure the functionality and yield of advanced 2.5D/3D packaging technologies. Key Responsibilities Defect Modeling & Analysis: Develop defect models for 2D structures (standard cells, FEOL/MEOL/BEOL) and 3D structures such as TSVs, interconnects, hybrid bonding, and chip stacking. Perform root-cause analyses of electrical, mechanical, and thermal defects in advanced packages and address them using design-for-test methods. Simulation & ATPG: Conduct SPICE simulations to evaluate circuit behavior under defect conditions and identify failure scenarios. Use EDA ATPG tools (or develop internal methods) to generate defect-oriented test patterns. A strong understanding of standard cell layout, parasitic extraction, and simulation is required. Testing & Probing Structures: Assess the influence of probing techniques and test structure designs on defect detection and reliability learning. Develop and implement methodologies leveraging test/probe structures to monitor process variations and enhance yield. Collaborate closely with internal partners (DPT Standard Cell, PE/Fab, QR) and external partners (EDA vendors). Research & Optimization: Implement advanced test methodologies for defect detection at both chip and package levels. Stay updated on evolving technologies and defect mechanisms in semiconductor manufacturing. Contribute to patents and publications in leading conferences and journals. Cross-Functional Collaboration: Approximately 75% of this role will focus on fundamental research, with ~30% involving collaboration across design, process, and manufacturing teams. The role demands a proactive mindset and flexibility to push solutions forward across geographies and stakeholders. Required Qualifications Education: Master’s or Ph.D. in Computer Engineering, Semiconductor Physics, or a related field. Experience: At least 15+ years of expertise in failure mechanisms, defect physics, testing, or reliability analysis for semiconductor devices, including 2D and 3D structures. Technical Skills: Proficiency with SPICE simulation tools (HSPICE, PSPICE, Spectre), LVS/DRC verification tools, and DFT/ATPG methodologies for packaging and advanced nodes. Programming or scripting skills (Python, Perl, C++) for automation and data analysis are required; experience with AI/ML for defect prediction is a plus. Domain Knowledge: Deep understanding of defect physics, testing/probing structures, and their impact on defect detection, characterization, and yield learning in advanced process nodes and 3D packaging. Familiarity with thermal and mechanical considerations in 3D integration. Industry Exposure: Demonstrated contributions through patents, publications, or conference presentations in defect modeling, reliability, or advanced packaging. Location San Jose, CA. Visa sponsorship may be considered for exceptional candidates. Why This Role? This is a career-defining opportunity to shape the methodologies and tools that will underpin the next decade of semiconductor innovation. Success requires technical expertise and the ability to bring forward new ideas, and to collaborate across diverse teams in San Jose, Taiwan, and Japan. Why TSMC? TSMC is the world’s leading semiconductor foundry, driving innovations that power AI, HPC, 5G, and beyond. By joining our team, you will gain access to the most advanced technologies in 2.5D/3D packaging and the chance to influence the direction of the global semiconductor industry. TSMC fosters an environment where bold ideas are welcomed, collaboration is global, and impact is tangible. This role offers the opportunity to solve challenging problems in defect modeling and testing and contribute to breakthroughs that define the future of electronics. Company Description As a trusted technology and capacity provider, TSMC is committed to a diverse workforce and equal employment opportunity for all individuals regardless of race, color, religion, gender, age, national origin, marital status, sexual orientation, gender identity, veteran status, genetic information, or any other characteristic protected by applicable law. TSMC is an equal opportunity employer prizing diversity and inclusion. If you require reasonable accommodation during the application or recruiting process, please notify us at View email address on click.appcast.io. Reasonable accommodations will be determined on a case-by-case basis. Pay Transparency / Benefits At TSMC, your base pay is only part of your total compensation. At the time of this posting, this role typically pays a base salary between $152,500 and $244,000 per year. The range reflects the minimum and maximum target for new hires. Actual pay may be more or less. Factors include skills, qualifications, education, experience, position level and location. Our total compensation package includes market-competitive pay, allowances, bonuses, and comprehensive benefits, with opportunities for development. #J-18808-Ljbffr TSMC