Analog Layout Engineer

Analog Layout Engineer

At Capgemini Engineering, we bring together a global team of engineers, scientists, and architects to help the world's most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.

Location: This is an onsite role based in Santa Clara, CA.

About the job you are considering: We are seeking an experienced Analog/RF Layout Designer to provide onsite support for advanced semiconductor nodes while partnering with a highly collaborative, global design and layout organization. In this role, you will contribute to cutting-edge analog and mixed-signal IP development, working across complex technologies such as FinFET and deep sub-micron processes. This is an excellent opportunity for a hands-on layout expert who thrives in technically challenging environments and enjoys end-to-end ownership from block-level design through top-level integration.

Your role: Independently develop block-level and IP-level analog/RF layouts, partnering closely with circuit designers and global layout teams to drive designs from concept to tape-out. Own floorplanning, placement, routing, and optimization for complex analog and mixed-signal blocks, including SerDes, ADC/DACs, PLLs, and related IPs. Lead and support top-level integration of multiple analog and mixed-signal blocks within larger SoCs. Apply deep expertise in advanced deep sub-micron and FinFET process technologies, incorporating fabrication, EM, ESD, latch-up, and reliability considerations into layouts. Resolve complex DRC, LVS, antenna, and verification issues, exercising strong technical judgment while collaborating across geographies and mentoring or guiding team members as a technical lead.

Your skills and experience: Bachelor's degree in Electrical Engineering, Electronics, or a related field. 6+ years of hands-on experience in analog and/or RF layout design (8+ years preferred). Proven experience with analog floor planning and layout for complex modules such as SerDes, ADC/DAC, PLLs, and similar high-speed or precision circuits. Strong understanding of analog layout best practices for deep sub-micron CMOS and FinFET technologies.

The base compensation range for this role in the posted location is: 97,700 - 203,800. Capgemini provides compensation range information in accordance with applicable national, state, provincial, and local pay transparency laws. The base compensation range listed for this position reflects the minimum and maximum target compensation Capgemini, in good faith, believes it may pay for the role at the time of this posting. This range may be subject to change as permitted by law. The actual compensation offered to any candidate may fall outside of the posted range and will be determined based on multiple factors legally permitted in the applicable jurisdiction. These may include, but are not limited to: Geographic location, Education and qualifications, Certifications and licenses, Relevant experience and skills, Seniority and performance, Market and business consideration, Internal pay equity. It is not typical for candidates to be hired at or near the top of the posted compensation range. In addition to base salary, this role may be eligible for additional compensation such as variable incentives, bonuses, or commissions, depending on the position and applicable laws. Capgemini offers a comprehensive, non-negotiable benefits package to all regular, full-time employees.

Important Notice: Compensation (including bonuses, commissions, or other forms of incentive pay) is not considered earned, vested, or payable until it becomes due under the terms of applicable plans or agreements and is subject to Capgemini's discretion, consistent with applicable laws. The Company reserves the right to amend or withdraw compensation programs at any time, within the limits of applicable legislation.

Disclaimers: Capgemini is an Equal Opportunity Employer encouraging inclusion in the workplace. Capgemini also participates in the Partnership Accreditation in Indigenous Relations (PAIR) program which supports meaningful engagement with Indigenous communities across Canada by promoting fairness, accessibility, inclusion and respect. We value the rich cultural heritage and contributions of Indigenous Peoples and actively work to create a welcoming and respectful environment. All qualified applicants will receive consideration for employment without regard to race, national origin, gender identity/expression, age, religion, disability, sexual orientation, genetics, veteran status, marital status or any other characteristic protected by law. This is a general description of the Duties, Responsibilities and Qualifications required for this position. Physical, mental, sensory or environmental demands may be referenced in an attempt to communicate the manner in which this position traditionally is performed. Whenever necessary to provide individuals with disabilities an equal employment opportunity, Capgemini will consider reasonable accommodations that might involve varying job requirements and/or changing the way this job is performed, provided that such accommodation does not pose an undue hardship. Capgemini is committed to providing reasonable accommodation during our recruitment process. If you need assistance or accommodation, please reach out to your recruiting contact.