Memory PHY RTL Design Engineer

WHAT YOU DO AT AMD CHANGES EVERYTHING

At AMD, our mission is to build great products that accelerate next‑generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.

THE ROLE

The Memory PHY team is looking for a passionate and experienced Design Engineer for RTL and firmware development of high-speed LPDDR, DDR IPs. Be a part of the definition, design and development phase of industry‑leading Memory PHYs and interface IP. This opportunity includes creation of new IO designs as well as working on multiple designs and enhancing methodologies in parallel.

THE PERSON

You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills and experience collaborating with engineers in different sites/timezones. You have strong analytical and problem‑solving skills and are willing to learn and ready to take on problems.

KEY RESPONSIBILITIES

RTL design for memory I/O PHY digital architecture development from pathfinding, coding, verification to physical implementation PHY link layer design, implementation & verification with analog and system architect PHY analog/digital co‑design Digital design and RTL coding Timing synthesis & drive physical implementation Collaborate with architects, hardware engineers, and firmware engineers to understand new features to be verified Estimate the time required to write the new feature tests and any required changes to the test environment Build the unit tests Debug design failures to determine the root cause; work with DV and firmware engineers to resolve design defects and correct any test issues

PREFERRED EXPERIENCE

Digital design engineering experience Experienced with Verilog, SystemVerilog, C, and C++ Excellent knowledge of Verilog, SystemVerilog and a scripting language; experience with Python, Perl and TCL is a plus Knowledge of clocking architectures, synchronization, and CDC methodology Experience with synthesis, timing closure SERDES, DDR, memory controller, or MAC design experience is preferred Proficient in debugging firmware and RTL code using simulation tools Strong understanding of computer organization/architecture Mixed signal RTL, low‑power design experience is a plus Exposure to leadership or mentorship is an asset

ACADEMIC CREDENTIALS

Bachelor’s or Master’s degree in computer engineering / electrical engineering

LOCATION

Boxborough, MA Benefits offered are described: AMD benefits at a glance. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process. #J-18808-Ljbffr Advanced Micro Devices