Senior Analog Design Engineer

Senior Analog Design Engineer – Hard IP & Test Chip Development Team Join Intel’s Central Engineering Group to design, develop, and optimize analog and mixed‑signal integrated circuits for high‑speed IO and die‑to‑die interfaces. Key Responsibilities Design & Development – Design, simulate, and optimize analog blocks (amplifiers, data converters, voltage regulators, PLLs, etc.) and create detailed transistor‑level architectures and layouts. Technical Leadership – Lead projects from specification to silicon validation, mentor junior engineers, conduct design reviews, and collaborate with cross‑functional teams across multiple process nodes. Validation & Optimization – Develop test plans, oversee silicon characterization, debug pre‑ and post‑silicon issues, and ensure designs meet performance, power, area, and industry specifications. Qualifications Minimum Qualifications Bachelor’s degree in Electrical Engineering, Electronics Engineering, or related field. 6+ years of analog/mixed‑signal circuit design experience for high‑speed SerDes or similar applications. Experience with PLL, CDR, CTLE, DFE, ADC, RX AFE, transmitter design, power delivery, IP floor planning, simulation of top‑level performance, and signal‑integrity analysis. Proficiency in high‑speed IO calibration, training algorithms, and protocols such as UCIE and PCIe (Gen5/Gen6/Gen7). Strong knowledge of core analog design principles, noise, linearity, matching, stability, and advanced FinFET CMOS processes. Hands‑on experience with Cadence Virtuoso/ADE, HSPICE (or equivalent), post‑silicon validation, and lab debugging. Preferred Qualifications Master’s degree in Electrical Engineering, Electronics Engineering, or related discipline. 7+ years of analog design for high‑speed SerDes or die‑to‑die applications, with deep understanding of transmitter/receiver loops and equalization. Knowledge of next‑generation standards such as PCIe 6.0, 800G Ethernet, or JESD. Experience with Verilog‑A modeling, MATLAB simulations, and automation scripting (Python, Tcl). Strong understanding of signal‑integrity concepts, channel modeling, and system‑level link analysis. Background in standard and advanced package technologies. Benefits & Compensation Competitive salary ranging from $190,610 to $269,100 USD. Stock bonuses and comprehensive benefit programs including health, retirement, and vacation. Hybrid work model with on‑site presence at Intel Phoenix, Arizona (minimum 4 days per week). About Intel Intel’s Central Engineering Group brings data‑driven engineering solutions across three pillars: Product Enablement, Custom ASIC, and Foundry Enablement. Equal Opportunity Employer All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr