IP Design Verification Engineer

Job Description Join Intel as a Mixed Signal Design Verification Engineer and play a critical role in shaping the future of cutting‑edge technology. In this position, you will ensure the functionality and performance of Intel's mixed signal components, which are essential to delivering world‑class semiconductor solutions. By collaborating with cross‑functional teams, you will drive the verification process to meet rigorous design, power, and performance specifications, ensuring Intel remains a leader in innovation. Your contributions will directly impact product reliability, efficiency, and overall design excellence on a global scale. Responsibilities Develop and execute comprehensive mixed‑signal IP verification plans to ensure designs meet specifications. Create and maintain test benches and verification environments using advanced methodologies such as UVM and OVM. Perform analog behavioral modeling to validate design functionality, timing, and power objectives. Identify, replicate, and debug pre‑silicon bugs, root‑cause issues, and drive corrective measures. Analyze coverage metrics to ensure verification completeness and propose improvements where needed. Collaborate across disciplines to refine verification strategies, optimize designs, and achieve project goals. Document test plans, methodologies, and results, and lead technical reviews with cross‑functional teams. Maintain and enhance existing verification infrastructure and methodologies to support evolving design challenges. Minimum Qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field, with 4 or more years of experience; Master's degree with 3 or more years of experience; or PhD with no experience. +3 years of experience in System Verilog, Verilog, and advanced verification methodologies such as UVM and OVM. Experience with industry‑standard EDA tools such as Synopsys VCS, Cadence Xcelium/JasperGold, or Mentor Questa. Analog behavioral modeling, high‑speed IO IP verification, or low‑power validation experience. Strong debugging skills in both analog and digital domains. Knowledge of PCIe and/or UCIe protocols. Test planning, test environment development, and test content development experience. Preferred Qualifications Experience collaborating in cross‑functional environments to solve complex problems. Proven ability to execute tasks with discipline and deliver results under tight timelines. Excellent written and verbal communication skills to document and present technical concepts effectively. Location Shift: Shift 1 (United States of America). Primary Location: US, Arizona, Phoenix. Additional Locations: US, California, Folsom; US, California, Santa Clara; US, Oregon, Hillsboro. Benefits We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range for jobs which could be performed in the US: $141,910.00‑200,340.00USD. The range displayed on this job posting reflects the minimum and maximum target compensation for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job‑related skills, experience, and relevant education or training. Work Model This role will require an on‑site presence. Job posting details (such as work model, location or time type) are subject to change. Intel is committed to Responsible Business Alliance (RBA) compliance and ethical hiring practices. We do not charge any fees during our hiring process. EEO Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. #J-18808-Ljbffr