Compensated Space FPGA Intern - HDL, Satellite Comm
CesiumAstro, Inc.
CesiumAstro is seeking Summer 2027 FPGA development interns to work on HDL-level FPGA systems for satellite communication. You will collaborate with engineers on design, verification, testing, and deployment across multiple clock domains and high-speed interfaces. Ideal candidates are enrolled in BS/MS/PhD programs in EE/CE with a GPA of 3.5+, hands-on FPGA project experience, and familiarity with Verilog/VHDL and FPGA tools. #J-18808-Ljbffr CesiumAstro, Inc.
Vacancy posted 19 hours ago
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