CPU Cache Subsystem Senior Design Manager

Lead and manage a team of design engineers working on CPU functional units, emphasizing on micro-architecture and RTL design for the next generation CPU subsystem.Review/propose performance enhancing micro-architecture features, and work with Software, Architect and Performance teams for trade-off studies. Communicate the pros and cons of micro-architecture enhancements.Deliver with plans on achieving project milestones and goals, towards a design that meets production quality on schedule.Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals.Focus on load-store-unit and cache subsystem design and optimizations with other parts of CPU to deliver best Performance, Power, Area (PPA).Minimum qualifications:Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing.Experience leading and managing teams for modern processor subsystems with high speed, lower power design.Experience with front-end quality checks (e.g., Lint, CDC/RDC).Preferred qualifications:Experience with ARM instruction set architecture.Experience with mobile CPU subsystem.Experience with mobile SOC architecture/integration.Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.In this role, you will contribute to all phases of complex designs of CPU subsystems from design specification to productization, including integration into target SOCs.You will lead and manage a front-end design team, collaborate with members of architecture, software, verification, power, DFT, physical design teams to define the micro-architecture and schedule in delivering high quality RTL that meets project goals.You will help your team grow and solve technical problems with innovative micro-architecture and practical logic solutions. You will be responsible for evaluating and deciding on the best design options with complexity, performance, power and area and schedule in mind.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $240000 - $333000 (USD) + 25% bonus target + equity + benefitsLearn more about benefits at Google.Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Austin, TX, USA; Mountain View, CA, USA; Portland, OR, USA; Poughkeepsie, NY, USA.Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience.15 years of experience in CPU design, including load-store unit logic/RTL and L2/L3 private/shared caches including micro-architecture definition and PPA processing.Experience leading and managing teams for modern processor subsystems with high speed, lower power design.Experience with front-end quality checks (e.g., Lint, CDC/RDC).