Physical Design Engineer, ASIC

Google, Sunnyvale, CA, USA Required qualifications Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with physical design from RTL to Graphic Data System II (GDSII), including synthesis, floor planning, place and route, and timing closure. Experience with scripting languages in one or more of the following: Perl, Python, or Tcl. Experience working with external partners on physical design (PD) closure. Experience with Synopsys/Cadence PnR tools and backend flows (e.g., LEC, PI/SI, DRC/LVS, etc.). Preferred qualifications Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture. 7 years of experience with physical design. Experience executing low-power physical design implementation using industry-standard EDA tools (Innovus/FC). Experience in sign-off convergence including Static timing analysis (STA), electrical checks, and physical verification. Experience in utilizing AI techniques for faster and optimal Physical Design Convergence (e.g., timing, floorplanning, power grid, and clock tree design). Understanding of DFT including Scan, MBIST and LBIST. Understanding of performance, power and area (PPA) trade-offs. About the job In this role, you’ll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting‑edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You’ll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML‑driven systems. As a Physical Design Engineer, you will collaborate closely with cross‑functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address complex physical implementation issues at advanced process nodes, utilizing micro‑architectural insights and practical logic circuit solutions. You will evaluate and optimize design options to deliver Performance, Power and Area (PPA) for the next generation of Tensor Processing Unit (TPU) blocks and sub‑chips. Responsibilities Perform physical design of complex blocks from Register‑Transfer Level (RTL) to Graphic Data System (GDS). Use problem‑solving, debugging skills and collaborate cross‑functional teams to achieve the best Power/Performance Analysis (PPA). Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized implementation and sign‑off domain. Work with architects and logic designers to drive architectural feasibility studies, develop timing, power and area design goals, and explore RTL/design trade‑offs for physical design closure. Compensation Individual pay is determined by factors including job‑related skills, experience, and relevant education or training. US: $138,000 - $198,000 (USD) + 15% bonus target + equity + benefits. Benefits Learn more about benefits at Google. Equal Employment Opportunity Google is proud to be an equal opportunity and affirmative action employer. We are committed to building a workforce that is representative of the users we serve, creating a culture of belonging, and providing an equal employment opportunity regardless of race, creed, color, religion, gender, sexual orientation, gender identity or expression, national origin, disability, age, genetic information, veteran status, marital status, pregnancy or related condition (including breastfeeding), expecting or parents‑to‑be, criminal histories consistent with legal requirements, or any other basis protected by law. See also Google's EEO Policy, Know your rights: workplace discrimination is illegal, Belonging at Google, and How we hire. Other Information Google is a global company and, in order to facilitate efficient collaboration and communication globally, English proficiency is a requirement for all roles unless stated otherwise in the job posting. Equity is granted exclusively and discretely by Alphabet Inc. on the basis of an agreement concluded between you and Alphabet Inc. Alphabet Inc. is your sole contractual partner with respect to equity grants. GSU grants are not guaranteed, are discretionary, are subject to approval by the Alphabet Inc. board of directors or its delegate, the terms of the relevant Alphabet Inc. stock plan, and your grant agreement. They have no impact on statutory payments. Current or past grants do not confer an acquired right. #J-18808-Ljbffr Google Inc.