Post-Silicon Validation, Principal Engineer

We Are 

Synopsys is the leader in engineering solutions from silicon to systems, enabling customers to rapidly innovate AI-powered products. We deliver industry-leading silicon design, IP, simulation and analysis solutions, and design services. We partner closely with our customers across a wide range of industries to maximize their R&D capability and productivity, powering innovation today that ignites the ingenuity of tomorrow. 

You Are 

You have spent a decade or more bringing silicon to life, and you know that the hardest problems do not show up in simulation. They show up in a customer's lab when the link will not train and nobody can explain why. You are the person who can connect observations across the analog, digital, protocol, package, and system domains, identify the most likely failure mechanisms, and drive the investigation to a defensible conclusion. When others see isolated symptoms, you see the larger technical story. 

You do not wait for perfect data. You work with what the silicon gives you, build the instrumentation to see what matters, and make the call on whether it ships. You have debugged enough high-speed links to know when the problem is in the analog, the protocol layer, the channel, or the way the customer assembled their interposer, and you can move between those domains without losing the thread. 

You write code because you have to. Not toy scripts, real validation frameworks in Python that other engineers depend on to characterize hundreds of test cases across process corners and data rates. You care about measurement integrity the way some people care about code coverage, because you have seen what happens when a team ships on bad data. 

At Synopsys, you will define how we validate UCIe die-to-die IP, own the silicon sign-off decision, and be the technical authority customers call when their multi-die product is stuck. 

What You'll Be Doing 

• Define the post-silicon validation and characterization strategy for UCIe-based die-to-die interface IP, including the methodology, coverage models, and sign-off criteria that determine whether silicon is ready to ship 
• Act as the final technical escalation point for silicon issues where root cause is not evident from the data, requiring you to evaluate intangibles across analog circuit behavior, package and interposer channel effects, link training firmware, protocol layer state machines, and system integration constraints 
• Lead the bring up and debug of customer silicon, working remotely or sometimes on-site in customer labs to resolve sideband and mainband link training failures, lane repair and reversal issues, degraded mode operation, and chiplet interoperability problems 
• Own the architecture and technical direction of the validation software platform in Python, including lab automation frameworks, data infrastructure, measurement correlation engines, and the instrumentation the organization depends on 
• Establish how die-to-die links are characterized when direct probe access is limited or unavailable, defining the use of on-die instrumentation, eye margining techniques, built-in monitors, and the correlation of that data back to bench measurements and simulation results 
• Drive validation programs that span multiple related areas of the business, coordinating across analog design, digital design, firmware, product engineering, applications, and marketing to reach shared technical outcomes and silicon readiness milestones 
• Represent Synopsys in technical engagements with major customers and, where appropriate, in industry and standards forums such as the UCIe Consortium

The Impact You Will Have 

• Resolve the class of silicon problems that would otherwise stall a program or delay a customer's multi-die product launch, directly affecting time-to-market and revenue outcomes 
• Raise the technical capability of the entire validation discipline through the methodology, tooling, and measurement standards you establish and the engineers you coach 
• Shape how the organization and industry approaches validation of next-generation UCIe data rates, packaging technologies, and chiplet topologies before those problems arrive, influencing roadmap and design decisions upstream 
• Deliver measurable impact on department targets including sign-off schedules, silicon respin avoidance, and the speed at which new IP reaches production readiness 
• Establish Synopsys as the credible technical partner customers turn to when their silicon does not work, strengthening customer relationships and competitive positioning 
• Feed silicon reality back into the design process, influencing architecture, circuit design, and packaging strategy with data that only post-silicon validation can provide

What You'll Need 

• Bachelor's degree in Electrical Engineering or Computer Engineering with a minimum of 10 years of related experience, or an advanced degree with a minimum of 8 years of related experience 
• Extensive expertise in post-silicon validation, characterization, and debug of high-speed mixed-signal interface IP across multiple silicon generations and process nodes 
• Authoritative command of the UCIe specification, including the PHY and D2D adapter layers, link initialization and training, sideband operation, lane repair and reversal, and the tradeoffs between standard and advanced packaging; direct UCIe or other die-to-die interface experience is strongly preferred, and deep high-speed SerDes experience is applicable 
• Recognized depth in high-speed link analysis, including equalization, jitter decomposition, crosstalk, and package, interposer, and substrate channel behavior, grounded in signals and systems concepts and transmission line theory 
• Advanced software architecture capability across multiple languages including Python, with experience building large-scale lab automation frameworks, data infrastructure, and measurement correlation systems 
• Expert-level command of high-speed oscilloscopes, BERTs, spectrum analyzers, and network analyzers, including understanding the limits of the instruments themselves and how to validate links that cannot be directly probed 
• Demonstrated success leading customer silicon bring up and debug engagements, working in customer lab environments and owning the technical relationship with external engineering teams; experience with software version control systems such as GitLab and with issue and task tracking through Jira and Confluence is a plus

Who You Are

• A technical expert who possesses extensive expertise and unique knowledge, and who uses it to contribute to the direction of the organization rather than only to the task at hand 
• The engineer others escalate to when the silicon does not behave and no one can explain why, able to diagnose root cause across circuit design, firmware, protocol, and system integration domains where the data is ambiguous 
• A credible, composed technical presence in front of major customers, effective at diagnosing unfamiliar hardware under schedule pressure and owning the technical relationship through resolution 
• An influencer who can bring adjacent groups along in ambiguous or sensitive situations without relying on positional authority, coordinating across design, firmware, product engineering, and applications to reach shared outcomes 
• A developer of people who coaches senior engineers, reviews and approves the work of Sr Staff and Staff engineers, and raises the standard of the validation discipline across the team 
• A rigorous professional with uncompromising standards for measurement integrity and data-driven conclusions, who knows the difference between silicon that is ready to ship and silicon that needs another pass

The Team You'll Be Part Of 

Your recruiter will share more about the team structure and mission during the interview process. 

Rewards and Benefits 

We offer a comprehensive range of health, wellness, and financial benefits to cater to your needs. Our total rewards include both monetary and non-monetary offerings. Your recruiter will provide more details about the salary range and benefits during the hiring process.