Sr. Staff Design Verification Engineer

Join d-Matrix and help build the future of AI inference. We’ve pioneered a memory-centric architecture that brings compute directly into memory, making AI faster, more energy efficient, and accessible on a global scale. From chips and software to rack-scale systems, our team is tackling some of AI infrastructure’s hardest challenges—and shipping breakthrough technology today. If you want to create what comes next and help make infinite inference possible, we’d love to hear from you.Our culture is built on respect, collaboration, and direct communication. We value humility, we believe our different perspectives lead to better solutions, and we’re looking for people who are driven by execution and energized by hard problems.Role Overviewd-Matrix is building a company and culture designed to last — one grounded in transparency, inclusiveness, and intellectual honesty, where continuous learning is part of the job. We've built the industry's first highly programmable in-memory computing architecture, applicable across a broad range of applications from cloud to edge. In this role, you'll work on a groundbreaking architecture alongside a highly experienced team that has a proven track record of building successful businesses. This is a unique opportunity to help shape a company at an early stage and grow into a future leader in an industry poised for global impact.What You Will DoDevelop and execute verification plans across the SoC/IP verification cycle, from architecture definition through tape-out and silicon bring-upBuild and maintain UVM/OVM-based verification environments for complex ASIC/SoC designsWrite and debug SystemVerilog testbenches, leveraging randomization, functional coverage, and assertion-based methodologiesDrive root-cause analysis and debug of verification failures in close collaboration with design and architecture teamsDefine and track coverage closure goals to ensure comprehensive verification sign-offPartner cross-functionally with design, architecture, and physical design teams to align verification strategy with tape-out schedulesContribute to the evolution of verification methodology and infrastructure to support next-generation in-memory computing architecturesWhat You Will BringBS in Electrical Engineering, Computer Science, or a related field with 12+ years of industry experience (MS preferred with 7+ years)Experience across the full SoC/IP verification cycle — from architecture through tape-out and bring-upHands-on ASIC/SoC design verification test development and debug experienceFluency with SystemVerilog (randomization, constraints, coverage, assertions) and verification methodologies such as UVM/OVM/VMMStrong problem-solving skills and a passion for tackling complex technical challenges, particularly in the AI domainPreferred QualificationsExperience with C/C++ and SystemCTrack record leading the creation and implementation of multiple SoC verification environments and driving tape-out effortsEqual Opportunity Employment Policyd-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation. Compensation Range: $175K - $265KLocationSanta ClaraEmployment TypeFull timeLocation TypeHybridDepartmentHardware EngineeringCompensation$175K – $265K • Offers Equity • Offers BonusThe pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role’s function and location, as well as the individual’s knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours.