High-Speed SI/PI Package Design Engineer

Location: On-site in Santa Clara, CA Job Type: Full-Time Company: Upscale AI Team Size: +100 employees Industry: High-Tech / Emerging Infrastructure Why join Upscale AI Upscale ai is an innovative high-tech startup delivering breakthrough infrastructure solutions in AI. With a rapidly growing team and cutting‑edge stack, we’re building for scale, resilience, and productivity. We’re looking for a smart, driven engineering professional to join our infrastructure team and help support a secure, scalable, and user‑friendly computing environment across the company. About the role: As a SI/PI Package Design Engineer focused on 224G Ethernet switches, your role is critical in enabling next‑generation ultra‑high‑speed networking products. You’ll be responsible for ensuring signal and power integrity across high‑speed interfaces in advanced package and PCB designs, pushing the limits of current technology. Key responsibilities: Signal Integrity (SI): Model and simulate high-speed interfaces (e.g., 224G-PAM4 SerDes). Perform channel simulations (TX-to-RX) across packages and PCBs. Work with IBIS-AMI, S-parameter models, and tools like Ansys HFSS, Keysight ADS, or Cadence Sigrity. Optimize interconnects to meet eye diagram, BER, and insertion/return loss targets. Validate compliance with standards like IEEE 802.3df/802.3dj and UAL. Power Integrity (PI): Analyze and design PDN (power delivery network) for core and I/O voltages. Ensure low impedance across required frequency range using de-cap optimization and VRM modeling. Use tools like PowerSI, PowerDC Package/Board Design Collaboration: Co‑design with package layout engineers (e.g., substrate, flip‑chip, organic packages). Define breakout strategies for dense BGA interfaces Guide stackup, via, and routing constraints in both package and board to enable 224G signaling. Cross‑Functional Collaboration: Interface with ASIC, system, layout, and test teams. Provide SI/PI guidelines and design constraints to enable electrical compliance. Support bring‑up and debug using scopes, VNAs, TDRs, etc. Skills & Tools: Simulation Tools:

SI: ADS, HFSS, ADK, HSPICE

PI: PowerSI, PowerDC Modeling: IBIS-AMI, S-parameters, RLGC models Analysis: Time‑domain and frequency‑domain signal analysis Crosstalk, jitter, eye closure, PDN impedance Fabrication Knowledge: HDI PCB and advanced package materials (e.g., Megtron 7, Ajinomoto) Low‑loss stackup optimization, via‑in‑pad, via stub mitigation Qualifications: BS/MS in Electrical Engineering or related field. 5+ years in Signal Integrity Title: Sr. High-Speed Package Design Engineer Compensation: Individual compensation will be commensurate with the candidate’s experience and aligned with UpscaleAI’s internal leveling guidelines and benchmarks. #J-18808-Ljbffr Upscaleai