Embedded Software Engineer

Embedded Software Engineer

Location: Sunnyvale, CA or Redmond, WA (100% Onsite)

Key Qualifications

This position is for a validation role with experience. Looking for someone who is hands-on in SoC validation and leads PnP & hardware/software testing and debugging:

• Expertise in Power and Performance characterization of SoC using Pre-Si & Post-Si tooling. Hands-on experience with Pre-Si tools like Synopsys Primetime Power Analysis and Post-Si tools like National Instruments Data Acquisition (NiDAQ) is required.
• Experience in C/C++ based embedded software development for bare metal, RTOS and Linux.
• Experience in ARM CPU, AMBA SoC architecture, boot flows, CPU & SoC initialization.
• Background in silicon bring-up and board debug
• Familiarity with IO protocols: MIPI, PCIe, USB, I2C, SPMI, UART, GPIO
• Understanding of common data structures, algorithms, Operating Systems concepts, and multi-threaded programming
• Experience with scripting languages such as Python, bash

Daily Tasks:

• Cross-correlate power estimation/measurements with the architectural specifications and drive HW/SW optimizations to meet the power targets.
• Lead and debug failures with multi-functional partner teams like: Software/Firmware, System Hardware and Silicon teams. Work with experts from cross functional teams to understand SoC and system behavior: OS kernel/driver, Silicon Validation (using unit-level IP & SoC tests), SoC IP integration and verification, FPGA Prototyping and Emulation (Palladium/ZeBu/Veloce), Systems Integration, board debug.
• Collaborate across architecture, design, and software teams to develop test plans. Debug and correlate silicon data. Create validation test plans, ensuring all key features are covered.
• Write low-level driver code as RTOS to configure and run various sub-systems (e.g. Camera, display, video encoders/decoders, PCIe, USB, machine learning etc). Bring up pre-Si prototypes and drive validation of functional & PnP features using bare-metal/RTOS workloads.
• Debug and bring-up of low power SOCs and lead validation testing of system hardware design. Efficiently narrow down failures from system-level to subsystem- and block-level using a range of debug tools and techniques (e.g. RTL Waveforms, Lauterbach, Transaction-level models) and lab equipment like Logic Analyzers & Scopes.