Senior SoC Compute/Memory Subsystem Architect

About The Role The CEG NAG (Networking Architecture Group) is Intel's premier team focused on defining the future of high-performance networking silicon. Our team architects next-generation networking solutions that enable hyperscale data centers, cloud infrastructure, and AI workloads to achieve unprecedented performance and efficiency. We specialize in IPU/DPU platforms, advanced packet processing architectures, and programmable networking technologies that form the backbone of modern distributed computing systems. Senior SoC Compute/Memory Subsystem Architect This role is responsible for end-to-end architecture of CPU clusters, cache hierarchies, coherency models, and memory subsystems. You will optimize system-level performance, scalability, power efficiency, and programmability while ensuring seamless interaction with networking, storage, and accelerator subsystems in hyperscale environments. What You’ll Do Compute Subsystem Architecture Define architecture for IPU compute complexes (e.g., ARM/x86 clusters), including core selection, scaling strategy, and configuration tradeoffs Architect compute subsystem roles (control plane, data plane assist, offload execution, management services) Drive compute architecture decisions balancing performance, power, and area Cache Hierarchy and Coherency Architecture Define and evolve multi-level cache hierarchy (private/shared caches, system-level cache) Architect coherency models across compute cores, accelerators, and IO subsystems (coherent vs non-coherent interactions) Evaluate tradeoffs between latency, bandwidth, scalability, and coherence domain complexity Memory Subsystem Architecture Architect system memory subsystems including: DDR / LPDDR interfaces Memory controllers and scheduling policies Bandwidth provisioning and scaling strategies Work with Performance architect in define memory access models for compute, network, and accelerator subsystems Ensure optimal balance between latency-sensitive control workloads and bandwidth-intensive datapath workloads IO Memory and Virtualization Architecture (SMMU/IOMMU) Define architecture for SMMU/IOMMU supporting virtualization-heavy IPU workloads Architect features such as: Multi-tenant isolation and security boundaries Shared vs isolated memory models Ensure efficient interaction between host, IPU/DPU compute, and offload engines System-Level Integration (Compute Network Storage) Architect integration between: Compute subsystem Network subsystem (packet processing pipelines) Storage and accelerator subsystems Optimize data movement across subsystems to minimize copies, latency, and bandwidth overhead Drive system architecture decisions for balanced SoC performance Power, Efficiency, and Scaling Strategy Define compute and memory strategies for power efficiency and DVFS scalability Architect mechanisms for: Memory bandwidth throttling / prioritization Per-subsystem scaling Optimize performance-per-watt at system level Multi-Generation Architecture Roadmap Lead long-term roadmap for compute and memory evolution across IPU/DPU product generations Define scaling strategies for: Core count and frequency Memory bandwidth and capacity Cache scaling and topology Ensure backward compatibility and smooth migration across product lines Cross-Functional Leadership Collaborate with teams across: Networking subsystem (NSS) SoC fabric/interconnect Firmware, OS, and drivers Validation and performance modeling and testing Drive architecture alignment and resolve cross-domain tradeoff Behavioral Traits Strategic thinker: Ability to define long-term architecture vision and align stakeholders Technical leadership: Influences across teams without direct authority Problem solver: Approaches complex system challenges with structured thinking Collaboration: Builds strong partnerships across engineering disciplines Customer-focused mindset: Translates real-world workload needs into solutions Adaptability: Navigates ambiguity and evolving technical requirements Ownership mindset: Drives initiatives from concept through execution Benefits Intel invests in our people and offers a complete and competitive package of benefits employees and their families through every stage of life. See Intel Benefits for more details. We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock bonuses, and benefit programs which include health, retirement, and vacation. Annual Salary Range: $164,470.00 - $269,100.00 USD (US locations). Individual pay is determined by location and other factors. Work Model for this Role This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. Job Requirements Minimum Qualifications: Batchelor's degree in Electrical Engineering, Computer Engineering, or a STEM related Field of Study. 7+ years of experience in SoC/CPU/memory subsystem architecture, CPU architecture and cache hierarchies. Experience with memory subsystems (DDR/HBM, controllers, QoS) and coherent/non-coherent interconnect architectures. Experience in system-level performance and PPA tradeoff analysis. Drive architecture definition from concept to silicon. Preferred Qualifications: Post Graduate degree in Electrical Engineering, Computer Engineering, or a STEM related Field of Study. ARM and x86 compute and memory subsystem experience, including NUMA systems, cache coherency, or large scale platform architectures. Experience with IPU/SmartNIC or accelerator-centric SoCs, particularly in cloud and hyperscale environments. Familiarity with PCIe, CXL, and memory semantics for high performance IO. Track record of multi-generation architectural ownership and mentoring other architects. Posting Statement All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance. Job Type Experienced Hire Shift Shift 1 (United States of America) Primary Location US, California, Santa Clara Additional Locations US, Arizona, Phoenix US, California, Folsom US, California, San Jose US, Colorado, Fort Collins US, Texas, Austin Business Group The Central Engineering Group (CEG) is Intel's data-driven organization that builds scalable engineering solutions across three pillars: Product Enablement (IP, tools, and methodologies), Custom ASIC (leveraging existing IP for custom silicon), and Foundry Enablement (supporting top customers and validating technologies). The team focuses on customer-driven, end-to-end solutions with short development cycles to deliver measurable business impact across Intel's product and foundry businesses. #J-18808-Ljbffr Intel