Senior Analog/RF Layout Engineer for SoC IPs

Capgemini is seeking an experienced Analog / RF Layout Designer in Santa Clara, California, to develop and optimize complex analog layouts. The role includes responsibilities such as driving layouts from concept to tape-out, overseeing placement and routing, and applying expertise in advanced technologies. The ideal candidate will have over 6 years of experience in analog/RF layout design and a Bachelor’s degree in Electrical Engineering. Capgemini offers comprehensive benefits including health insurance and retirement plans. #J-18808-Ljbffr