Physical Design Methodology Staff Engineer

ADVANCE YOUR CAREER. ADVANCE THE WORLD.At AMD, we believe technology can change lives for the better. It can heal us, entertain us, and make us more connected, productive, and understanding of the world around us. And we’re looking for talent who feel the same: people who want to leave the planet better than they found it, those who don’t shy away from humanity’s challenges but are determined to help solve them.AMD is powering the next generation of supercomputing, high-performance computing, cloud, and AI. Whether you’re designing next-gen processors, enabling AI breakthroughs, or creating go-to-market plans, every role at AMD contributes to something bigger — technology that moves the world forward.THE ROLEWe are seeking a Physical Design Methodology Staff Engineer to serve as the technical backbone of our high-performance core team. In this role, you will move beyond standard implementation to focus on the "how" of physical design. You will own the optimization of our EDA tool-chain, developing and refining the methodologies that enable our CPU cores to hit aggressive PPA (Power, Performance, and Area) targets. You will act as a power-user and flow-architect, bridging the gap between raw EDA tool capabilities and the complex requirements of GHz-class silicon.THE PERSONYou are an EDA-centric engineer who views the design flow as a system to be tuned, automated, and perfected. You are not just a user of tools; you are an expert in how tool algorithms, constraints, and physical parameters interact to produce optimal silicon. If you are driven by the challenge of reducing turnaround time, improving design predictability, and pushing EDA tools to their absolute limits, you are the ideal candidate for this role.KEY RESPONSIBILITIESFlow Architecture: Design, implement, and maintain end-to-end physical implementation flows (Synthesis through Signoff) that prioritize scalability, reproducibility, and high QoR.EDA Tool Optimization: Act as the primary interface with EDA vendors to drive tool adoption, evaluate new features, and troubleshoot complex tool-behavior issues.Methodology Development: Develop and deploy advanced scripting frameworks (Tcl/Python) to automate design space exploration, ECO implementation, and multi-corner timing closure.PPA Optimization: Systematically analyze and tune tool settings—including placement density, routing congestion management, and clock tree synthesis (CTS) strategies—to meet aggressive frequency and power targets.Signoff Integration: Build and refine automated signoff loops (STA, IR/EM, Physical Verification) to ensure high-confidence tape-outs with minimal iterations.Constraint Engineering: Develop and validate complex SDC constraints, ensuring that tool-driven optimizations are aligned with architectural intent and physical realities.Data-Driven Analysis: Utilize big-data approaches to analyze design metrics across multiple iterations, identifying trends in tool performance and implementing corrective methodology improvements.PREFERRED EXPERIENCEEDA & Methodology ExpertiseTool Mastery: Expert-level proficiency in industry-standard physical design platforms (e.g., Synopsys Fusion Compiler/ICC2, Cadence Innovus).Scripting & Automation: Advanced Tcl/Python/Perl skills; proven ability to build custom tool wrappers, automated debug utilities, and flow-management scripts.Flow Customization: Experience in customizing tool-specific APIs to handle unique design challenges, such as custom cell integration or non-standard floorplanning requirements.QoR Tuning: Demonstrated success in "tuning the engine"—adjusting tool-specific switches, constraints, and optimization strategies to resolve timing, power, or congestion bottlenecks.Technical DepthAdvanced Node Implementation: Deep understanding of the physical effects at 7nm/5nm/3nm nodes and how to configure EDA tools to mitigate parasitic, crosstalk, and LDE (Layout Dependent Effect) issues.Signoff Methodology: Mastery of the signoff ecosystem (PrimeTime SI, RedHawk-SC, Voltus, Calibre); experience in building "push-button" signoff flows that minimize manual intervention.Clocking & Power Flows: Expertise in configuring advanced CTS methodologies and power-aware implementation flows (e.g., UPF/CPF-driven design, multi-Vt optimization).Constraint Management: Deep knowledge of MMMC (Multi-Mode Multi-Corner) environments and the ability to manage complex timing exceptions in high-frequency CPU designs.ACADEMIC CREDENTIALS:MS or PhD in Electrical Engineering, Computer Engineering, or a related field (or equivalent industry experience).LOCATION:Austin, TXThis role is not eligible for visa sponsorship.Benefits offered are described: AMD benefits at a glance.AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.This posting is for an existing vacancy.