Senior Analog/Mixed-Signal ASIC Layout Architect

Overview Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit Overview Draper is an independent, nonprofit research and development company headquartered in Cambridge, MA. The 2,000+ employees of Draper tackle important national challenges with a promise of delivering successful and usable solutions. From military defense and space exploration to biomedical engineering, lives often depend on the solutions we provide. Our multidisciplinary teams of engineers and scientists work in a collaborative environment that inspires the cross-fertilization of ideas necessary for true innovation. For more information about Draper, visit Job Description Summary We are seeking a motivated individual to join the analog mixed signal (AMS) ASIC team at Draper. The physical silicon design group is responsible for creating complex analog layouts from schematics in collaboration with other members of our team. These layouts are used in ASICs for national security, biomedical, and space applications. While we are seeking a senior level engineer, considerations will be made at all levels for particularly capable applicants. A successful candidate will assist ASIC development through creating custom analog layouts, floor planning entire chips, high level problem solving, and executing tape outs. The ideal applicant is capable of tackling most issues independently, communicating effectively with team members across different disciplines, and has a desire to learn new techniques and methods. The candidate must have an understanding of silicon processing and its effect on circuit performance. The ability to understand and communicate about basic analog circuits is also desired. Reticle design and/or MPW aggregation is also of interest. While hybrid or remote work may be available, this position will have mandatory on-site work. Duties/Responsibilities Job Description: Design and simulate circuits at transistor-level to implement architecture and requirement specifications Contribute to system-level design Optimize hardware designs for performance, power, and cost Evaluate the hardware feasibility of complex algorithms and requirements Independently contribute to complex chip architectures and designs Independently drive solutions to complex problems - develop requirements, propose ways forward when customer requirements are unclear or incomplete, and adapt appropriately to changes in requirements Contribute to business development and proposal activities Develop, document, and teach best practices to less experienced engineers Perform or guide physical layout, including floor-planning, and simulate circuits using extracted parasitics. Perform other duties as assigned Skills/Abilities Proficiency in integrated circuit design Understanding of integrated circuits, semiconductors, and general computer architecture Ability to write detailed design specifications Ability to manage small technical teams Excellent verbal and written communication skills Excellent mathematical skills Excellent organizational skills and attention to detail Excellent time management skills with the proven ability to meet deadlines Strong analytical and problem-solving skills Ability to prioritize tasks Demonstrate strong organization, planning, and time management skills to achieve program goals Education Requires a bachelor's degree in Engineering, or related field. Masters degree preferred. Experience Requires 5-7 years of experience with a bachelor's degree, or 3-5 years of experience with a master's degree, or 0-2 years of experience with a PhD in ASIC Hardware Engineering or related. Additional Job Description Additional Job Description: Experience with low power circuit design Experience with CMOS advanced nodes below 32nm Experience with radiation-hardened electronics Experience with the Cadence (Virtuoso, Pegasus), Siemens (Calibre), and Keysight (SOS) toolsets. Proficiency in implementing analog designs into full custom layout. PLLs, DACs/ADCs, high speed SerDes, bandgaps, ESD/IO, and more. Ability to recognize layouts vulnerable to failure and ways to fix. ESD/LU, DFM, etc. Fluent in layout effects and how circuit performance can be affected. NW proximity, length-of-diffusion, implant shadowing, EM/IR, self-heating, coupling capacitance, matching techniques, etc. Experience with understanding and debugging DRC, LVS, PM, and other physical verification tools and methodologies. Ability to operate independently with some oversight, attempting to solve problems by themselves before asking for help. Experience with chip level/top down floor planning. Ability to communicate technical information and issues across disciplines. Preferred experience with automation tools (Cadence ModGen/autorouter/EAD, Innovus, etc), and methods for transferring data between domains (abstract/LEF). Understanding of how revision control software operates (SOS, git, SVN, etc) Able to motivate themselves and operate independently. Ability to mentor others and willingness to be mentored. Experience operating in a Linux environment. Preferred experience with scripting (SKILL, SVRF, tcl). Experience with FinFET processes, 22nm to 7nm and below. Preference for experience with GAAFET processes and/or photonics processes. High preference for experience with reticle design and/or MPW aggregation. Applicants selected for this position will be required to obtain and maintain a government security clearance Connect With Draper for Future Opportunities! If you don't find the right posting in our Career Opportunities, you may submit your resume for future consideration. Job Location - City: Cambridge Job Location - State: Massachusetts Job Location - Postal Code: 02139-3563 The US base salary range for this full-time position is $82,300.00 - $220,000.00 Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the minimum and maximum target salaries for the position across all US locations. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Union ranges will be in compliance with the collective bargaining agreement's approved rates by location and role. Your recruiter can share more about the specific salary range for your preferred location during the hiring process. Please note that the compensation details listed in US role postings reflect the base salary only, and does not include bonuses or benefits. Our work is very important to us, but so is our life outside of work. Draper supports many programs to improve work-life balance including workplace flexibility, employee clubs ranging from photography to yoga, health and finance workshops, off site social events and discounts to local museums and cultural activities. If this specific job opportunity and the chance to work at a nationally renowned R&D innovation company appeals to you, apply now Draper is committed to creating an inclusive environment. We understand the value of inclusivity and its impact on a high-performance culture. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, disability, age, sexual orientation, national origin, veteran status, or genetic information. Draper is committed to providing access, equal opportunity, and reasonable accommodation for individuals with disabilities in employment, its services, programs, and activities. To request reasonable accommodation, please contact View email address on click.appcast.io. #J-18808-Ljbffr Draper