Physical Design Engineer

N2P Systems Sunnyvale, California, United States 10+ years $100 - $110 USD / hr N2P Systems is seeking an experienced Physical Design Engineer to join our enterprise technology delivery team in Sunnyvale, California, United States. At N2P Systems, you will put 10+ years of hands-on experience with ASIC/SoC Physical Design, RTL Synthesis and Timing Optimization to work on mission-critical enterprise systems. This is an existing contract, on-site vacancy with N2P Systems. N2P Systems is seeking an experienced Physical Design Engineer to support advanced ASIC and SoC development for a leading technology organization in Sunnyvale, California. This on-site contract opportunity requires strong front-end design experience, particularly in RTL synthesis, synthesis optimization, physical design flows, and placement optimization. The engineer will contribute to achieving performance, power, and area (PPA) targets while improving implementation quality and supporting design convergence throughout the chip development lifecycle. N2P Systems uses AI to help screen and assess applications for this role. N2P Systems is an enterprise technology consulting and digital solutions firm operating across Canada, the United States and India. Key Responsibilities Drive RTL synthesis and synthesis optimization to achieve performance, power, and area (PPA) objectives. Perform floorplanning for complex ASIC and SoC designs, considering timing, congestion, and power distribution requirements. Collaborate with RTL design engineers to improve RTL quality, synthesis results, and implementation efficiency. Analyze synthesized netlists to identify optimization opportunities and improve design quality. Work with architecture, RTL, verification, and physical design teams to support design convergence. Identify implementation bottlenecks and recommend improvements to facilitate timing closure. Participate in design reviews and contribute to improvements in design methodologies and implementation processes. Required Skills & Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field. 10+ years of industry experience in ASIC/SoC physical design. Strong hands-on experience with RTL synthesis and timing optimization. Solid experience in floorplanning for advanced technology nodes. Strong understanding of netlist optimization and physical implementation methodologies. Experience collaborating with RTL and design teams to improve design quality and implementation efficiency. Ability to work effectively across multidisciplinary silicon engineering teams. Preferred Qualifications Experience with industry-standard EDA tools for synthesis and physical design. Strong understanding of timing, congestion, power, and area optimization techniques. Experience with placement optimization and PPA improvement methodologies. Background in high-performance CPU, GPU, AI/ML, or networking SoC designs. Role Pre-Screening Criteria Applicants will be asked to answer the following qualifying questions when applying for this position: 1 Do you have 10+ years of hands-on experience in ASIC/SoC physical design, including RTL synthesis and timing optimization? 2 Do you have hands-on experience with floorplanning, netlist optimization, and physical implementation for complex ASIC/SoC designs? 3 Have you worked on placement optimization and PPA (Power, Performance, and Area) optimization in advanced semiconductor design projects? 4 Are you legally authorized to work in the United States? We consider candidates with valid work authorization under any visa category, except those relying on OPT. Target Tech Stack ASIC/SoC Physical Design RTL Synthesis Timing Optimization Floorplanning Netlist Optimization Physical Implementation 10+ Years of Industry Experience in ASIC/SoC Physical Design Industry-Standard EDA Tools Placement Optimization Power, Congestion, and Area Optimization High-Performance CPU, GPU, AI/ML, or Networking SoC Design ASIC Physical Design SoC Physical Design Synthesis Optimization Physical Design Flow Timing Closure Power Optimization Performance Optimization Area Optimization PPA Optimization EDA Tools Congestion Optimization Power Distribution RTL Quality Optimization High-Performance SoC Design CPU GPU AI/ML SoC Networking SoC 10+ Years of Industry Experience Power Distribution Optimization High-Performance CPU Design GPU Design AI/ML SoC Design Networking SoC Design Location Sunnyvale, California, United States Employment Type Contract Work Arrangement Onsite Experience Level 10+ years Compensation $100 - $110 USD / hr Domain Focus General Engineering #J-18808-Ljbffr