Design Verification Engineer

Multiple Design Verification (DV) Opportunities - U.S. Based (Hybrid & Onsite) We are partnered with several cutting-edge semiconductor client s who are actively hiring Design Verification Engineer s across a range of domains. These roles are NOT fully remot e - each has a defined hybrid or onsite expectation, outlined below If you’re a DV engineer exploring your next move, chances ar e one of these aligns we ll Bay Area, CA – Onsite (4x/week) DV Engineer – AI Native • Deep experience verifying AI/ML accelerators, LLMs, TPUs, etc. • 2–13 years of experience Bay Area, CA – Hybrid DV Engineers – Multiple Domains Looking for DV engineers with experience in one or more of the following: • CPU / Processor • Networking • PCIe / Ethernet • AI Accelerators • UCIe / CXL • NoC / NIC • Memory Controller