AMS Verification Engineer

HCLTech is looking for a highly talented and self-motivated AMS Verification Engineer to join it in advancing the technological world through innovation and creativity.

Job Title: AMS Verification Engineer

Job ID: 155227

Position Type: Full Time

Location: Redmond, WA - Remote

We are looking for an experienced AMS Verification Engineer to support Analog Mixed Signal (AMS) verification of a DAC channel and its digital interconnect (Channel Block).

The engineer will work across analog behavioral models and digital RTL to build and execute the AMS verification environment and drive verification through SoC tapeout.

Key Responsibilities

• Develop and work with Verilog-A / Verilog-AMS models for DAC IP. The initial DAC IP model will be provided.
• Integrate the analog DAC model with digital RTL to simulate and analyze mixed-signal interactions.
• Define and execute the AMS verification test plan.
• Develop test environments to simulate and verify mixed-signal design behavior.
• Perform SoC-level AMS verification of the DAC channel and associated digital interconnect.
• Analyze simulation results and compare them against target functionality and specifications.
• Debug complex analog/digital interactions, simulation failures, and functional issues.
• Work closely with RTL, analog, and verification teams to drive issues to closure and support tapeout.

Required Qualifications

• Hands-on SoC tapeout experience .
• Strong experience with SoC-level AMS verification .
• Experience developing Verilog-AMS (VAMS) / Verilog-A behavioral models .
• Strong SystemVerilog and UVM verification environment experience.
• Experience integrating analog behavioral models with digital RTL .
• Strong understanding of mixed-signal simulation and verification methodologies.
• Extensive experience in debugging AMS simulations and analog/digital interaction issues .

Nice to Have

• Experience verifying DACs or similar mixed-signal IP .
• Experience with AMS simulation and debug tools from Cadence, Synopsys, or Siemens EDA .
• Understanding of analog/digital interfaces and mixed-signal SoC architecture.
• Experience taking AMS verification from test planning through tapeout/signoff .

Pay and Benefits

Pay Range Minimum: $95000/Year

Pay Range Maximum: $192000/Year

HCLTech is an equal opportunity employer, committed to providing equal employment opportunities to all applicants and employees regardless of race, religion, sex, color, age, national origin, pregnancy, sexual orientation, physical disability or genetic information, military or veteran status, or any other protected classification, in accordance with federal, state, and/or local law. Should any applicant have concerns about discrimination in the hiring process, they should provide a detailed report of those concerns to View email address on click.appcast.io for investigation.

A candidate’s pay within the range will depend on their skills, experience, education, and other factors permitted by law. This role may also be eligible for performance-based bonuses subject to company policies. In addition, this role is eligible for the following benefits subject to company policies: medical, dental, vision, pharmacy, life, accidental death & dismemberment, and disability insurance; employee assistance program; 401(k) retirement plan; 10 days of paid time off per year (some positions are eligible for need-based leave with no designated number of leave days per year); and 10 paid holidays per year

How You’ll Grow

At HCLTech, we offer continuous opportunities for you to find your spark and grow with us. We want you to be happy and satisfied with your role and to really learn what type of work sparks your brilliance the best. Throughout your time with us, we offer transparent communication with senior-level employees, learning and career development programs at every level, and opportunities to experiment in different roles or even pivot industries. We believe that you should be in control of your career with unlimited opportunities to find the role that fits you best.